Merge pull request #458 from paulusmack/fixes

Fixes for bugs found in dcache, loadstore1 and execute1.

Author: paulusmack

dcache.vhdl

@@ -1121,9 +1121,9 @@ begin
             if r0.req.sync = '1' then
                 req_op_sync <= '1';
             elsif r0.req.touch = '1' then
-                if access_ok = '1' and is_hit = '0' and nc = '0' then
+                if access_ok = '1' and (is_hit or hit_reload) = '0' and nc = '0' then
                     req_op_load_miss <= '1';
-                elsif access_ok = '1' and is_hit = '1' and nc = '0' then
+                elsif access_ok = '1' and (is_hit or hit_reload) = '1' and nc = '0' then
                     -- Make this OP_LOAD_HIT so the PLRU gets updated
                     req_op_load_hit <= '1';
                 else
@@ -1632,13 +1632,6 @@ begin
                             r1.reloading <= '1';
                             r1.write_tag <= '1';
                             ev.load_miss <= '1';
-
-                            -- If this is a touch, complete the instruction
-                            if req.touch = '1' then
-                                r1.full <= '0';
-                                r1.slow_valid <= '1';
-                                r1.ls_valid <= '1';
-                            end if;
                         else
                             r1.state <= NC_LOAD_WAIT_ACK;
                         end if;
@@ -1710,6 +1703,13 @@ begin
 			r1.wb.adr <= next_row_wb_addr(r1.wb.adr);
 		    end if;
 
+                    -- If this is a touch, complete the instruction
+                    if r1.full = '1' and r1.req.touch = '1' then
+                        r1.full <= '0';
+                        r1.slow_valid <= '1';
+                        r1.ls_valid <= '1';
+                    end if;
+
 		    -- Incoming acks processing
 		    if wishbone_in.ack = '1' then
                         r1.rows_valid(to_integer(r1.store_row(ROW_LINEBITS-1 downto 0))) <= '1';

execute1.vhdl

@@ -1442,8 +1442,8 @@ begin
                     if e_in.spr_select.ispmu = '0' then
                         case e_in.spr_select.sel is
                             when SPRSEL_LOGR =>
-                                if e_in.insn(16) = '0' then
-                                    v.se.inc_loga := '1';
+                                if e_in.insn(16) = '1' then
+                                    v.se.inc_loga := '1';       -- reading LOG_DATA
                                 end if;
                             when others =>
                         end case;
@@ -1525,6 +1525,7 @@ begin
                         when SPRSEL_DEC =>
                             v.se.write_dec := '1';
                         when SPRSEL_LOGR =>
+                            -- must be writing LOG_ADDR; LOG_DATA is readonly
                             v.se.write_loga := '1';
                         when SPRSEL_CFAR =>
                             v.se.write_cfar := '1';
@@ -1624,7 +1625,7 @@ begin
             -- misaligned prefixed instructions, which has higher priority than
             -- other facility unavailable interrupts.
             v.exception := '1';
-            v.ic := x"b";
+            v.ic := std_ulogic_vector(to_unsigned(FSCR_PREFIX, 4));
             v.e.intr_vec := 16#f60#;
             v.se.write_ic := '1';
 
@@ -1666,23 +1667,23 @@ begin
             ctrl.fscr_scv = '0' then
             -- Facility unavailable for scv instruction
             v.exception := '1';
-            v.ic := x"c";
+            v.ic := std_ulogic_vector(to_unsigned(FSCR_SCV, 4));
             v.e.intr_vec := 16#f60#;
             v.se.write_ic := '1';
 
         elsif ex1.msr(MSR_PR) = '1' and e_in.uses_tar = '1' and
             ctrl.fscr_tar = '0' then
             -- Facility unavailable for TAR access
             v.exception := '1';
-            v.ic := x"8";
+            v.ic := std_ulogic_vector(to_unsigned(FSCR_TAR, 4));
             v.e.intr_vec := 16#f60#;
             v.se.write_ic := '1';
 
         elsif ex1.msr(MSR_PR) = '1' and e_in.uses_dscr = '1' and
             ctrl.fscr_dscr = '0' then
             -- Facility unavailable for DSCR access
             v.exception := '1';
-            v.ic := x"2";
+            v.ic := std_ulogic_vector(to_unsigned(FSCR_DSCR, 4));
             v.e.intr_vec := 16#f60#;
             v.se.write_ic := '1';
 
@@ -1733,6 +1734,7 @@ begin
             v.prefixed := e_in.prefixed;
             v.insn := e_in.insn;
             v.prefix := e_in.prefix;
+            v.advance_nia := '0';
         end if;
 
         lv := Execute1ToLoadstore1Init;

loadstore1.vhdl

@@ -951,6 +951,13 @@ begin
                 if r1.req.read_spr = '1' then
                     v.addr0 := sprval;
                 end if;
+                -- tlbie has req.dc_req set in order to send the TLB probe to
+                -- the dcache, but since there is no acknowledgement to wait for,
+                -- clear req.dc_req so that loadstore1_3 completes when the MMU
+                -- is finished.
+                if r1.req.mmu_op = '1' then
+                    v.req.dc_req := '0';
+                end if;
 
                 -- Work out load formatter controls for next cycle
                 for i in 0 to 7 loop