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1 parent c84f2c7 commit 31c022aCopy full SHA for 31c022a
llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
@@ -481,7 +481,7 @@ let Predicates = [IsISAFuture] in {
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RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
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def DMSHA3HASH :
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- XForm_ATp2_SR5<31, 15, 177, (outs dmrprc:$ATp), (ins dmrprc:$ATpi , u5imm:$SR),
+ XForm_ATp2_SR5<31, 15, 177, (outs dmrp:$ATp), (ins dmrp:$ATpi , u5imm:$SR),
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"dmsha3hash $ATp, $SR",
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[(set v2048i1:$ATp, (int_ppc_mma_dmsha3hash v2048i1:$ATpi, timm:$SR))]>,
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RegConstraint<"$ATpi = $ATp">, NoEncode<"$ATpi">;
@@ -626,10 +626,10 @@ let Predicates = [IsISAFuture] in {
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(DMSHA2HASH dmr:$AT, dmr:$AB, 1)>;
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def : InstAlias<"dmsha3dw $ATp",
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- (DMSHA3HASH dmrprc:$ATp, 0)>;
+ (DMSHA3HASH dmrp:$ATp, 0)>;
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def : InstAlias<"dmcryshash $ATp",
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- (DMSHA3HASH dmrprc:$ATp, 12)>;
+ (DMSHA3HASH dmrp:$ATp, 12)>;
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def : InstAlias<"dmxxsha3512pad $AT, $XB, $E",
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(DMXXSHAPAD dmr:$AT, vsrc:$XB, 0, u1imm:$E, 0)>;
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -1140,6 +1140,6 @@ def PPCRegDMRpRCAsmOperand : AsmOperandClass {
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let PredicateMethod = "isDMRpRegNumber";
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}
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-def dmrprc : RegisterOperand<DMRpRC> {
+def dmrp : RegisterOperand<DMRpRC> {
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let ParserMatchClass = PPCRegDMRpRCAsmOperand;
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