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[SOL] Implement hints of stack stores and loads (#163)
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3 files changed

+205
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‎llvm/lib/Target/SBF/SBFInstrInfo.cpp

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -114,6 +114,41 @@ void SBFInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
114114
llvm_unreachable("Can't store this register to stack slot");
115115
}
116116

117+
Register SBFInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
118+
int &FrameIndex,
119+
unsigned &MemBytes) const {
120+
switch (MI.getOpcode()) {
121+
default:
122+
break;
123+
case SBF::STD_V2:
124+
case SBF::STD_V1:
125+
MemBytes = 8;
126+
if (MI.getOperand(0).isReg() && MI.getOperand(1).isFI() &&
127+
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
128+
FrameIndex = MI.getOperand(1).getIndex();
129+
return MI.getOperand(0).getReg();
130+
}
131+
break;
132+
case SBF::STW32_V2:
133+
case SBF::STW32_V1:
134+
MemBytes = 4;
135+
if (MI.getOperand(0).isReg() && MI.getOperand(1).isFI() &&
136+
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
137+
FrameIndex = MI.getOperand(1).getIndex();
138+
return MI.getOperand(0).getReg();
139+
}
140+
break;
141+
}
142+
143+
return 0;
144+
}
145+
146+
Register SBFInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
147+
int &FrameIndex) const {
148+
unsigned MemBytes = 0;
149+
return isStoreToStackSlot(MI, FrameIndex, MemBytes);
150+
}
151+
117152
void SBFInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
118153
MachineBasicBlock::iterator I,
119154
Register DestReg, int FI,
@@ -136,6 +171,41 @@ void SBFInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
136171
llvm_unreachable("Can't load this register from stack slot");
137172
}
138173

174+
Register SBFInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
175+
int &FrameIndex,
176+
unsigned &MemBytes) const {
177+
switch (MI.getOpcode()) {
178+
default:
179+
break;
180+
case SBF::LDD_V2:
181+
case SBF::LDD_V1:
182+
MemBytes = 8;
183+
if (MI.getOperand(0).isReg() && MI.getOperand(1).isFI() &&
184+
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
185+
FrameIndex = MI.getOperand(1).getIndex();
186+
return MI.getOperand(0).getReg();
187+
}
188+
break;
189+
case SBF::LDW32_V2:
190+
case SBF::LDW32_V1:
191+
MemBytes = 4;
192+
if (MI.getOperand(0).isReg() && MI.getOperand(1).isFI() &&
193+
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
194+
FrameIndex = MI.getOperand(1).getIndex();
195+
return MI.getOperand(0).getReg();
196+
}
197+
break;
198+
}
199+
200+
return 0;
201+
}
202+
203+
Register SBFInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
204+
int &FrameIndex) const {
205+
unsigned MemBytes = 0;
206+
return isLoadFromStackSlot(MI, FrameIndex, MemBytes);
207+
}
208+
139209
bool SBFInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
140210
MachineBasicBlock *&TBB,
141211
MachineBasicBlock *&FBB,

‎llvm/lib/Target/SBF/SBFInstrInfo.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,18 @@ class SBFInstrInfo : public SBFGenInstrInfo {
6868
std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
6969
Register Reg) const override;
7070

71+
Register isStoreToStackSlot(const MachineInstr &MI,
72+
int &FrameIndex) const override;
73+
74+
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
75+
unsigned &MemBytes) const override;
76+
77+
Register isLoadFromStackSlot(const MachineInstr &MI,
78+
int &FrameIndex) const override;
79+
80+
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
81+
unsigned &MemBytes) const override;
82+
7183
private:
7284
bool HasExplicitSignExt;
7385
bool NewMemEncoding;

‎llvm/unittests/Target/SBF/SBFInstrInfoTest.cpp

Lines changed: 123 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -125,6 +125,129 @@ TEST_P(SBFInstrInfoTest, IsAddImmediate) {
125125
ASSERT_FALSE(MI7Res.has_value());
126126
}
127127

128+
TEST_P(SBFInstrInfoTest, IsStoreToStackSlot) {
129+
const SBFInstrInfo *TII = ST->getInstrInfo();
130+
DebugLoc DL;
131+
132+
MachineInstr *MI = BuildMI(*MF, DL, TII->get(SBF::STD_V2))
133+
.addReg(SBF::R1, getKillRegState(true))
134+
.addFrameIndex(10)
135+
.addImm(0)
136+
.getInstr();
137+
int FI = 0;
138+
unsigned Mem = 0;
139+
auto MI1Res = TII->isStoreToStackSlot(*MI, FI, Mem);
140+
EXPECT_EQ(MI1Res.id(), SBF::R1);
141+
EXPECT_EQ(FI, 10);
142+
EXPECT_EQ(Mem, 8u);
143+
144+
MI = BuildMI(*MF, DL, TII->get(SBF::STD_V1))
145+
.addReg(SBF::R2, getKillRegState(true))
146+
.addFrameIndex(17)
147+
.addImm(0)
148+
.getInstr();
149+
FI = 0;
150+
Mem = 0;
151+
MI1Res = TII->isStoreToStackSlot(*MI, FI, Mem);
152+
EXPECT_EQ(MI1Res.id(), SBF::R2);
153+
EXPECT_EQ(FI, 17);
154+
EXPECT_EQ(Mem, 8u);
155+
156+
MI = BuildMI(*MF, DL, TII->get(SBF::STW32_V2))
157+
.addReg(SBF::R2, getKillRegState(true))
158+
.addFrameIndex(15)
159+
.addImm(0)
160+
.getInstr();
161+
FI = 0;
162+
Mem = 0;
163+
MI1Res = TII->isStoreToStackSlot(*MI, FI, Mem);
164+
EXPECT_EQ(MI1Res.id(), SBF::R2);
165+
EXPECT_EQ(FI, 15);
166+
EXPECT_EQ(Mem, 4u);
167+
168+
MI = BuildMI(*MF, DL, TII->get(SBF::STW32_V1))
169+
.addReg(SBF::R5, getKillRegState(true))
170+
.addFrameIndex(18)
171+
.addImm(0)
172+
.getInstr();
173+
FI = 0;
174+
Mem = 0;
175+
MI1Res = TII->isStoreToStackSlot(*MI, FI, Mem);
176+
EXPECT_EQ(MI1Res.id(), SBF::R5);
177+
EXPECT_EQ(FI, 18);
178+
EXPECT_EQ(Mem, 4u);
179+
180+
MI = BuildMI(*MF, DL, TII->get(SBF::LDW32_V1), SBF::R1)
181+
.addReg(SBF::R5, getKillRegState(true))
182+
.addFrameIndex(18)
183+
.addImm(0)
184+
.getInstr();
185+
FI = 0;
186+
Mem = 0;
187+
MI1Res = TII->isStoreToStackSlot(*MI, FI, Mem);
188+
EXPECT_EQ(MI1Res.id(), 0u);
189+
}
190+
191+
TEST_P(SBFInstrInfoTest, IsLoadFromStackSlot) {
192+
const SBFInstrInfo *TII = ST->getInstrInfo();
193+
DebugLoc DL;
194+
195+
MachineInstr *MI = BuildMI(*MF, DL, TII->get(SBF::LDD_V2), SBF::R1)
196+
.addFrameIndex(10)
197+
.addImm(0)
198+
.getInstr();
199+
int FI = 0;
200+
unsigned Mem = 0;
201+
auto MI1Res = TII->isLoadFromStackSlot(*MI, FI, Mem);
202+
EXPECT_EQ(MI1Res.id(), SBF::R1);
203+
EXPECT_EQ(FI, 10);
204+
EXPECT_EQ(Mem, 8u);
205+
206+
MI = BuildMI(*MF, DL, TII->get(SBF::LDD_V1), SBF::R2)
207+
.addFrameIndex(17)
208+
.addImm(0)
209+
.getInstr();
210+
FI = 0;
211+
Mem = 0;
212+
MI1Res = TII->isLoadFromStackSlot(*MI, FI, Mem);
213+
EXPECT_EQ(MI1Res.id(), SBF::R2);
214+
EXPECT_EQ(FI, 17);
215+
EXPECT_EQ(Mem, 8u);
216+
217+
MI = BuildMI(*MF, DL, TII->get(SBF::LDW32_V2), SBF::R2)
218+
.addFrameIndex(15)
219+
.addImm(0)
220+
.getInstr();
221+
FI = 0;
222+
Mem = 0;
223+
MI1Res = TII->isLoadFromStackSlot(*MI, FI, Mem);
224+
EXPECT_EQ(MI1Res.id(), SBF::R2);
225+
EXPECT_EQ(FI, 15);
226+
EXPECT_EQ(Mem, 4u);
227+
228+
MI = BuildMI(*MF, DL, TII->get(SBF::LDW32_V1))
229+
.addReg(SBF::R5, getKillRegState(true))
230+
.addFrameIndex(18)
231+
.addImm(0)
232+
.getInstr();
233+
FI = 0;
234+
Mem = 0;
235+
MI1Res = TII->isLoadFromStackSlot(*MI, FI, Mem);
236+
EXPECT_EQ(MI1Res.id(), SBF::R5);
237+
EXPECT_EQ(FI, 18);
238+
EXPECT_EQ(Mem, 4u);
239+
240+
MI = BuildMI(*MF, DL, TII->get(SBF::STD_V2))
241+
.addReg(SBF::R5, getKillRegState(true))
242+
.addFrameIndex(18)
243+
.addImm(0)
244+
.getInstr();
245+
FI = 0;
246+
Mem = 0;
247+
MI1Res = TII->isLoadFromStackSlot(*MI, FI, Mem);
248+
EXPECT_EQ(MI1Res.id(), 0u);
249+
}
250+
128251
} // namespace
129252

130253
INSTANTIATE_TEST_SUITE_P(SBFTest, SBFInstrInfoTest, testing::Values("sbf"));

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