[SOL] Remove expand in order option (#135)

Author: LucasSte

llvm/lib/Target/SBF/CMakeLists.txt

@@ -27,7 +27,6 @@ add_llvm_target(SBFCodeGen
   SBFMCInstLower.cpp
   SBFPreserveDIType.cpp
   SBFRegisterInfo.cpp
-  SBFSelectionDAGInfo.cpp
   SBFSubtarget.cpp
   SBFTargetMachine.cpp
   SBFMIPeephole.cpp

llvm/lib/Target/SBF/SBFISelLowering.cpp

@@ -29,10 +29,6 @@ using namespace llvm;
 
 #define DEBUG_TYPE "sbf-lower"
 
-static cl::opt<bool> SBFExpandMemcpyInOrder("sbf-expand-memcpy-in-order",
-  cl::Hidden, cl::init(false),
-  cl::desc("Expand memcpy into load/store pairs in order"));
-
 static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg) {
   MachineFunction &MF = DAG.getMachineFunction();
   DAG.getContext()->diagnose(
@@ -153,38 +149,20 @@ SBFTargetLowering::SBFTargetLowering(const TargetMachine &TM,
   setMinFunctionAlignment(Align(8));
   setPrefFunctionAlignment(Align(8));
 
-  if (SBFExpandMemcpyInOrder) {
-    // LLVM generic code will try to expand memcpy into load/store pairs at this
-    // stage which is before quite a few IR optimization passes, therefore the
-    // loads and stores could potentially be moved apart from each other which
-    // will cause trouble to memcpy pattern matcher inside kernel eBPF JIT
-    // compilers.
-    //
-    // When -sbf-expand-memcpy-in-order specified, we want to defer the expand
-    // of memcpy to later stage in IR optimization pipeline so those load/store
-    // pairs won't be touched and could be kept in order. Hence, we set
-    // MaxStoresPerMem* to zero to disable the generic getMemcpyLoadsAndStores
-    // code path, and ask LLVM to use target expander EmitTargetCodeForMemcpy.
-    MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 0;
-    MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 0;
-    MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 0;
-    MaxLoadsPerMemcmp = 0;
-  } else {
-    // A syscall consumes at least 10 CUs, so we should only invoke it when
-    // the number of instructions is at least 10.
-
-    // Memset translates to stdw or stdxw, so the maximum should be 10.
-    MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 10;
-    // Each store in memcpy follows a load, so the maximum is 5.
-    MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 5;
-    // Each store in memmove follows a load, so the maximum is 5.
-    MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 5;
-    // Memcmp expands to three instructions for each load:
-    // 1. One load for each pointer being compared.
-    // 2. One jne for each load.
-    // The limit here should be three, since 3*3 = 9;
-    MaxLoadsPerMemcmp = MaxLoadsPerMemcmpOptSize = 3;
-  }
+  // A syscall consumes at least 10 CUs, so we should only invoke it when
+  // the number of instructions is at least 10.
+
+  // Memset translates to stdw or stdxw, so the maximum should be 10.
+  MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 10;
+  // Each store in memcpy follows a load, so the maximum is 5.
+  MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 5;
+  // Each store in memmove follows a load, so the maximum is 5.
+  MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 5;
+  // Memcmp expands to three instructions for each load:
+  // 1. One load for each pointer being compared.
+  // 2. One jne for each load.
+  // The limit here should be three, since 3*3 = 9;
+  MaxLoadsPerMemcmp = MaxLoadsPerMemcmpOptSize = 3;
 
   // CPU/Feature control
   HasAlu32 = STI.getHasAlu32();
@@ -915,8 +893,6 @@ const char *SBFTargetLowering::getTargetNodeName(unsigned Opcode) const {
     return "SBFISD::BR_CC";
   case SBFISD::Wrapper:
     return "SBFISD::Wrapper";
-  case SBFISD::MEMCPY:
-    return "SBFISD::MEMCPY";
   }
   return nullptr;
 }
@@ -966,37 +942,6 @@ SBFTargetLowering::EmitSubregExt(MachineInstr &MI, MachineBasicBlock *BB,
   return PromotedReg2;
 }
 
-MachineBasicBlock *
-SBFTargetLowering::EmitInstrWithCustomInserterMemcpy(MachineInstr &MI,
-                                                     MachineBasicBlock *BB)
-                                                     const {
-  MachineFunction *MF = MI.getParent()->getParent();
-  MachineRegisterInfo &MRI = MF->getRegInfo();
-  MachineInstrBuilder MIB(*MF, MI);
-  unsigned ScratchReg;
-
-  // This function does custom insertion during lowering SBFISD::MEMCPY which
-  // only has two register operands from memcpy semantics, the copy source
-  // address and the copy destination address.
-  //
-  // Because we will expand SBFISD::MEMCPY into load/store pairs, we will need
-  // a third scratch register to serve as the destination register of load and
-  // source register of store.
-  //
-  // The scratch register here is with the Define | Dead | EarlyClobber flags.
-  // The EarlyClobber flag has the semantic property that the operand it is
-  // attached to is clobbered before the rest of the inputs are read. Hence it
-  // must be unique among the operands to the instruction. The Define flag is
-  // needed to coerce the machine verifier that an Undef value isn't a problem
-  // as we anyway is loading memory into it. The Dead flag is needed as the
-  // value in scratch isn't supposed to be used by any other instruction.
-  ScratchReg = MRI.createVirtualRegister(&SBF::GPRRegClass);
-  MIB.addReg(ScratchReg,
-             RegState::Define | RegState::Dead | RegState::EarlyClobber);
-
-  return BB;
-}
-
 MachineBasicBlock *
 SBFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                                                MachineBasicBlock *BB) const {
@@ -1008,7 +953,6 @@ SBFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                        Opc == SBF::Select_32 ||
                        Opc == SBF::Select_32_64);
 
-  bool isMemcpyOp = Opc == SBF::MEMCPY;
   bool isAtomicFence = Opc == SBF::ATOMIC_FENCE;
 
 #ifndef NDEBUG
@@ -1018,12 +962,10 @@ SBFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                        Opc == SBF::Select_Ri_32_64);
 
 
-  assert((isSelectRROp || isSelectRIOp || isMemcpyOp || isAtomicFence) &&
+  assert((isSelectRROp || isSelectRIOp || isAtomicFence) &&
          "Unexpected instr type to insert");
 #endif
 
-  if (isMemcpyOp)
-    return EmitInstrWithCustomInserterMemcpy(MI, BB);
 
   if (isAtomicFence) {
     // this is currently a nop

llvm/lib/Target/SBF/SBFISelLowering.h

@@ -28,7 +28,6 @@ enum NodeType : unsigned {
   SELECT_CC,
   BR_CC,
   Wrapper,
-  MEMCPY,
 };
 }
 
@@ -159,10 +158,6 @@ class SBFTargetLowering : public TargetLowering {
   unsigned EmitSubregExt(MachineInstr &MI, MachineBasicBlock *BB, unsigned Reg,
                          bool isSigned) const;
 
-  MachineBasicBlock * EmitInstrWithCustomInserterMemcpy(MachineInstr &MI,
-                                                        MachineBasicBlock *BB)
-                                                        const;
-
 };
 }
 

llvm/lib/Target/SBF/SBFInstrInfo.cpp

@@ -51,95 +51,6 @@ void SBFInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     llvm_unreachable("Impossible reg-to-reg copy");
 }
 
-void SBFInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
-  Register DstReg = MI->getOperand(0).getReg();
-  Register SrcReg = MI->getOperand(1).getReg();
-  uint64_t CopyLen = MI->getOperand(2).getImm();
-  uint64_t Alignment = MI->getOperand(3).getImm();
-  Register ScratchReg = MI->getOperand(4).getReg();
-  MachineBasicBlock *BB = MI->getParent();
-  DebugLoc dl = MI->getDebugLoc();
-  unsigned LdOpc, StOpc;
-
-#define MEM_SWITCH(X) \
-LdOpc = NewMemEncoding ? SBF::LD##X##_V2 : SBF::LD##X##_V1; \
-StOpc = NewMemEncoding ? SBF::ST##X##_V2 : SBF::ST##X##_V1;
-
-  unsigned BytesPerOp = std::min(static_cast<unsigned>(Alignment), 8u);
-  switch (Alignment) {
-  case 1:
-    MEM_SWITCH(B)
-    break;
-  case 2:
-    MEM_SWITCH(H)
-    break;
-  case 4:
-    MEM_SWITCH(W)
-    break;
-  case 8:
-  case 16:
-    MEM_SWITCH(D)
-    break;
-  default:
-    llvm_unreachable("unsupported memcpy alignment");
-  }
-
-  unsigned IterationNum = (CopyLen >> Log2_64(BytesPerOp));
-  for (unsigned I = 0; I < IterationNum; ++I) {
-    BuildMI(*BB, MI, dl, get(LdOpc))
-        .addReg(ScratchReg, RegState::Define)
-        .addReg(SrcReg)
-        .addImm(I * BytesPerOp);
-    BuildMI(*BB, MI, dl, get(StOpc))
-        .addReg(ScratchReg, RegState::Kill)
-        .addReg(DstReg)
-        .addImm(I * BytesPerOp);
-  }
-
-  unsigned BytesLeft = CopyLen - IterationNum * BytesPerOp;
-  unsigned Offset;
-  if (BytesLeft == 0) {
-    BB->erase(MI);
-    return;
-  }
-
-  if (BytesLeft < 2) {
-    Offset = CopyLen - 1;
-    MEM_SWITCH(B)
-  } else if (BytesLeft <= 2) {
-    Offset = CopyLen - 2;
-    MEM_SWITCH(H)
-  } else if (BytesLeft <= 4) {
-    Offset = CopyLen - 4;
-    MEM_SWITCH(W)
-  } else if (BytesLeft <= 8) {
-    Offset = CopyLen - 8;
-    MEM_SWITCH(D)
-  } else {
-    llvm_unreachable("There cannot be more than 8 bytes left");
-  }
-
-  BuildMI(*BB, MI, dl, get(LdOpc))
-      .addReg(ScratchReg, RegState::Define)
-      .addReg(SrcReg)
-      .addImm(Offset);
-  BuildMI(*BB, MI, dl, get(StOpc))
-      .addReg(ScratchReg, RegState::Kill)
-      .addReg(DstReg)
-      .addImm(Offset);
-
-  BB->erase(MI);
-}
-
-bool SBFInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
-  if (MI.getOpcode() == SBF::MEMCPY) {
-    expandMEMCPY(MI);
-    return true;
-  }
-
-  return false;
-}
-
 void SBFInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator I,
                                        Register SrcReg, bool IsKill, int FI,

llvm/lib/Target/SBF/SBFInstrInfo.h

@@ -33,8 +33,6 @@ class SBFInstrInfo : public SBFGenInstrInfo {
                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
                    bool KillSrc) const override;
 
-  bool expandPostRAPseudo(MachineInstr &MI) const override;
-
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI, Register SrcReg,
                            bool isKill, int FrameIndex,
@@ -61,7 +59,6 @@ class SBFInstrInfo : public SBFGenInstrInfo {
   void initializeTargetFeatures(bool HasExplicitSext, bool NewMemEncoding);
 
 private:
-  void expandMEMCPY(MachineBasicBlock::iterator) const;
   bool HasExplicitSignExt;
   bool NewMemEncoding;
 };

llvm/lib/Target/SBF/SBFInstrInfo.td

@@ -28,10 +28,6 @@ def SDT_SBFBrCC         : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
                                                SDTCisVT<3, OtherVT>]>;
 def SDT_SBFWrapper      : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
                                                SDTCisPtrTy<0>]>;
-def SDT_SBFMEMCPY       : SDTypeProfile<0, 4, [SDTCisVT<0, i64>,
-                                               SDTCisVT<1, i64>,
-                                               SDTCisVT<2, i64>,
-                                               SDTCisVT<3, i64>]>;
 
 def SBFcall         : SDNode<"SBFISD::CALL", SDT_SBFCall,
                              [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
@@ -47,9 +43,6 @@ def SBFbrcc         : SDNode<"SBFISD::BR_CC", SDT_SBFBrCC,
 
 def SBFselectcc     : SDNode<"SBFISD::SELECT_CC", SDT_SBFSelectCC, [SDNPInGlue]>;
 def SBFWrapper      : SDNode<"SBFISD::Wrapper", SDT_SBFWrapper>;
-def SBFmemcpy       : SDNode<"SBFISD::MEMCPY", SDT_SBFMEMCPY,
-                             [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
-                              SDNPMayStore, SDNPMayLoad]>;
 def SBFIsLittleEndian : Predicate<"CurDAG->getDataLayout().isLittleEndian()">;
 def SBFIsBigEndian    : Predicate<"!CurDAG->getDataLayout().isLittleEndian()">;
 def SBFHasALU32 : Predicate<"Subtarget->getHasAlu32()">;
@@ -1463,11 +1456,3 @@ let Predicates = [SBFHasALU32, SBFNewMemEncoding] in {
   def : Pat<(i64 (extloadi32 ADDRri:$src)),
             (SUBREG_TO_REG (i64 0), (LDW32_V2 ADDRri:$src), sub_32)>;
 }
-
-let usesCustomInserter = 1, isCodeGenOnly = 1 in {
-    def MEMCPY : Pseudo<
-      (outs),
-      (ins GPR:$dst, GPR:$src, i64imm:$len, i64imm:$align, variable_ops),
-      "#memcpy dst: $dst, src: $src, len: $len, align: $align",
-      [(SBFmemcpy GPR:$dst, GPR:$src, imm:$len, imm:$align)]>;
-}

llvm/lib/Target/SBF/SBFSelectionDAGInfo.cpp

@@ -20,12 +20,6 @@ namespace llvm {
 class SBFSelectionDAGInfo : public SelectionDAGTargetInfo {
 public:
   SBFSelectionDAGInfo() {}
-  SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
-                                  SDValue Chain, SDValue Dst, SDValue Src,
-                                  SDValue Size, Align Alignment,
-                                  bool isVolatile, bool AlwaysInline,
-                                  MachinePointerInfo DstPtrInfo,
-                                  MachinePointerInfo SrcPtrInfo) const override;
 
   unsigned getCommonMaxStoresPerMemFunc() const {
     return 4;