Skip to content

Commit fcad39e

Browse files
committed
[SOL] Properly lower CTTZ and CTLZ in SBF (#143)
* Revert "[SOL] Revert 'Emit table lookup from TargetLowering::expandCTTZ()'" This reverts commit 9e0bc0c. * Expand correctly * Revert test setup
1 parent f2b6263 commit fcad39e

File tree

11 files changed

+353
-17
lines changed

11 files changed

+353
-17
lines changed

llvm/lib/Target/SBF/SBFISelLowering.cpp

Lines changed: 36 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ SBFTargetLowering::SBFTargetLowering(const TargetMachine &TM,
5454
setOperationAction(ISD::BRIND, MVT::Other, Expand);
5555
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
5656

57-
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
57+
setOperationAction({ISD::GlobalAddress, ISD::ConstantPool}, MVT::i64, Custom);
5858

5959
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
6060
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
@@ -102,6 +102,10 @@ SBFTargetLowering::SBFTargetLowering(const TargetMachine &TM,
102102
setOperationAction(ISD::SRL_PARTS, VT, Expand);
103103
setOperationAction(ISD::SRA_PARTS, VT, Expand);
104104
setOperationAction(ISD::CTPOP, VT, Expand);
105+
setOperationAction(ISD::CTTZ, VT, Expand);
106+
setOperationAction(ISD::CTLZ, VT, Expand);
107+
setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
108+
setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
105109

106110
setOperationAction(ISD::SETCC, VT, Expand);
107111
setOperationAction(ISD::SELECT, VT, Expand);
@@ -122,11 +126,6 @@ SBFTargetLowering::SBFTargetLowering(const TargetMachine &TM,
122126
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
123127
}
124128

125-
setOperationAction(ISD::CTTZ, MVT::i64, Expand);
126-
setOperationAction(ISD::CTLZ, MVT::i64, Expand);
127-
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
128-
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
129-
130129
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
131130
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
132131
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
@@ -290,6 +289,8 @@ SDValue SBFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
290289
return LowerGlobalAddress(Op, DAG);
291290
case ISD::SELECT_CC:
292291
return LowerSELECT_CC(Op, DAG);
292+
case ISD::ConstantPool:
293+
return LowerConstantPool(Op, DAG);
293294
case ISD::ATOMIC_SWAP:
294295
case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
295296
case ISD::ATOMIC_CMP_SWAP:
@@ -882,16 +883,40 @@ const char *SBFTargetLowering::getTargetNodeName(unsigned Opcode) const {
882883
return nullptr;
883884
}
884885

886+
static SDValue getTargetNode(GlobalAddressSDNode *N, const SDLoc &DL, EVT Ty,
887+
SelectionDAG &DAG, unsigned Flags) {
888+
return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
889+
}
890+
891+
static SDValue getTargetNode(ConstantPoolSDNode *N, const SDLoc &DL, EVT Ty,
892+
SelectionDAG &DAG, unsigned Flags) {
893+
return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(),
894+
N->getOffset(), Flags);
895+
}
896+
897+
template <class NodeTy>
898+
SDValue SBFTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
899+
unsigned Flags) const {
900+
SDLoc DL(N);
901+
902+
SDValue GA = getTargetNode(N, DL, MVT::i64, DAG, Flags);
903+
904+
return DAG.getNode(SBFISD::Wrapper, DL, MVT::i64, GA);
905+
}
906+
885907
SDValue SBFTargetLowering::LowerGlobalAddress(SDValue Op,
886908
SelectionDAG &DAG) const {
887-
auto N = cast<GlobalAddressSDNode>(Op);
909+
GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
888910
assert(N->getOffset() == 0 && "Invalid offset for global address");
889911

890-
SDLoc DL(Op);
891-
const GlobalValue *GV = N->getGlobal();
892-
SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64);
912+
return getAddr(N, DAG);
913+
}
893914

894-
return DAG.getNode(SBFISD::Wrapper, DL, MVT::i64, GA);
915+
SDValue SBFTargetLowering::LowerConstantPool(llvm::SDValue Op,
916+
llvm::SelectionDAG &DAG) const {
917+
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
918+
919+
return getAddr(N, DAG);
895920
}
896921

897922
unsigned

llvm/lib/Target/SBF/SBFISelLowering.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,9 +76,14 @@ class SBFTargetLowering : public TargetLowering {
7676

7777
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
7878
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
79+
80+
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
7981
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
8082
SDValue LowerATOMICRMW(SDValue Op, SelectionDAG &DAG) const;
8183

84+
template<class NodeTy>
85+
SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
86+
8287
// Lower the result values of a call, copying them out of physregs into vregs
8388
SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
8489
CallingConv::ID CallConv, bool IsVarArg,

llvm/lib/Target/SBF/SBFInstrInfo.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1245,6 +1245,12 @@ def : Pat<(SBFWrapper tglobaladdr:$in),
12451245
(HOR_addr (MOV_32_64_addr tglobaladdr:$in),
12461246
tglobaladdr:$in)>, Requires<[SBFNoLddw]>;
12471247

1248+
def : Pat<(SBFWrapper tconstpool:$in), (LD_imm64 tconstpool:$in)>,
1249+
Requires<[SBFHasLddw]>;
1250+
def : Pat<(SBFWrapper tconstpool:$in),
1251+
(HOR_addr (MOV_32_64_addr tconstpool:$in),
1252+
tconstpool:$in)>, Requires<[SBFNoLddw]>;
1253+
12481254
// SBFv2 sign extension
12491255
def : Pat<(i64 (sext GPR32:$src)),
12501256
(MOV_32_64 GPR32:$src)>, Requires<[SBFExplicitSignExt]>;

llvm/lib/Target/SBF/SBFMCInstLower.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,9 @@ void SBFMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
7474
case MachineOperand::MO_GlobalAddress:
7575
MCOp = LowerSymbolOperand(MO, GetGlobalAddressSymbol(MO));
7676
break;
77+
case MachineOperand::MO_ConstantPoolIndex:
78+
MCOp = LowerSymbolOperand(MO, Printer.GetCPISymbol(MO.getIndex()));
79+
break;
7780
}
7881

7982
OutMI.addOperand(MCOp);

llvm/test/CodeGen/BPF/cttz-ctlz.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,3 @@
1-
; XFAIL: *
21
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
32
; RUN: llc < %s -mtriple=bpf -mcpu=v1 | FileCheck %s
43

llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2-
; XFAIL: *
32
; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64ZBB
43
; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32ZBB
54

llvm/test/CodeGen/RISCV/rv32xtheadbb.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,3 @@
1-
; XFAIL: *
21
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
32
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
43
; RUN: | FileCheck %s -check-prefixes=RV32I

llvm/test/CodeGen/RISCV/rv64xtheadbb.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,3 @@
1-
; XFAIL: *
21
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
32
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
43
; RUN: | FileCheck %s -check-prefix=RV64I

llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,3 @@
1-
; XFAIL: *
21
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
32
; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
43

llvm/test/CodeGen/RISCV/shl-cttz.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,3 @@
1-
; XFAIL: *
21
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
32
; RUN: llc -mtriple=riscv32 -mattr=+m < %s \
43
; RUN: | FileCheck %s -check-prefix=RV32I

0 commit comments

Comments
 (0)