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[WebAssembly] [Codegen] Add pattern for relaxed min max from fminimum/fmaximum over v4f32 and v2f64 (llvm#162948)
Related to llvm#55932
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‎llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp‎

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@@ -183,6 +183,11 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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for (auto T : {MVT::i32, MVT::i64})
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setOperationAction(Op, T, Custom);
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if (Subtarget->hasRelaxedSIMD()) {
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setOperationAction(
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{ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXNUM, ISD::FMAXIMUMNUM},
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{MVT::v4f32, MVT::v2f64}, Legal);
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}
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// SIMD-specific configuration
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if (Subtarget->hasSIMD128()) {
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‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td‎

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@@ -1742,6 +1742,23 @@ defm SIMD_RELAXED_FMIN :
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defm SIMD_RELAXED_FMAX :
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RelaxedBinary<F64x2, int_wasm_relaxed_max, "relaxed_max", 0x110>;
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let Predicates = [HasRelaxedSIMD] in {
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foreach vec = [F32x4, F64x2] in {
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defvar relaxed_min = !cast<NI>("SIMD_RELAXED_FMIN_"#vec);
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defvar relaxed_max = !cast<NI>("SIMD_RELAXED_FMAX_"#vec);
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// Transform standard fminimum/fmaximum to relaxed versions
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def : Pat<(vec.vt (fminnum (vec.vt V128:$lhs), (vec.vt V128:$rhs))),
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(relaxed_min V128:$lhs, V128:$rhs)>;
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def : Pat<(vec.vt (fminimumnum (vec.vt V128:$lhs), (vec.vt V128:$rhs))),
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(relaxed_min V128:$lhs, V128:$rhs)>;
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def : Pat<(vec.vt (fmaxnum (vec.vt V128:$lhs), (vec.vt V128:$rhs))),
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(relaxed_max V128:$lhs, V128:$rhs)>;
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def : Pat<(vec.vt (fmaximumnum (vec.vt V128:$lhs), (vec.vt V128:$rhs))),
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(relaxed_max V128:$lhs, V128:$rhs)>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Relaxed rounding q15 multiplication
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//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s -mtriple=wasm32-unknown-unknown -mattr=+simd128,+relaxed-simd | FileCheck %s
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; Test that fmaxnum and fmaximumnum get transformed to relaxed_max
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target triple = "wasm32"
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define <4 x float> @test_maxnum_f32x4(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_maxnum_f32x4:
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; CHECK: .functype test_maxnum_f32x4 (v128, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: local.get 1
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; CHECK-NEXT: f32x4.relaxed_max
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; CHECK-NEXT: # fallthrough-return
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%result = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b)
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ret <4 x float> %result
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}
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define <4 x float> @test_maximumnum_f32x4(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_maximumnum_f32x4:
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; CHECK: .functype test_maximumnum_f32x4 (v128, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: local.get 1
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; CHECK-NEXT: f32x4.relaxed_max
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; CHECK-NEXT: # fallthrough-return
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%result = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> %a, <4 x float> %b)
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ret <4 x float> %result
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}
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define <2 x double> @test_maxnum_f64x2(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: test_maxnum_f64x2:
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; CHECK: .functype test_maxnum_f64x2 (v128, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: local.get 1
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; CHECK-NEXT: f64x2.relaxed_max
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; CHECK-NEXT: # fallthrough-return
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%result = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %a, <2 x double> %b)
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ret <2 x double> %result
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}
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define <2 x double> @test_minimumnum_f64x2(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: test_minimumnum_f64x2:
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; CHECK: .functype test_minimumnum_f64x2 (v128, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: local.get 1
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; CHECK-NEXT: f64x2.relaxed_max
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; CHECK-NEXT: # fallthrough-return
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%result = call <2 x double> @llvm.maximumnum.v2f64(<2 x double> %a, <2 x double> %b)
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ret <2 x double> %result
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}
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declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>)
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declare <4 x float> @llvm.maximumnum.v4f32(<4 x float>, <4 x float>)
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declare <2 x double> @llvm.maxnum.v2f64(<2 x double>, <2 x double>)
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declare <2 x double> @llvm.maximumnum.v2f64(<2 x double>, <2 x double>)

‎llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s -mtriple=wasm32-unknown-unknown -mattr=+simd128,+relaxed-simd | FileCheck %s
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; Test that fminnum and fminimumnum get transformed to relaxed_min
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target triple = "wasm32"
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define <4 x float> @test_minnum_f32x4(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_minnum_f32x4:
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; CHECK: .functype test_minnum_f32x4 (v128, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: local.get 1
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; CHECK-NEXT: f32x4.relaxed_min
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; CHECK-NEXT: # fallthrough-return
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%result = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b)
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ret <4 x float> %result
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}
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define <4 x float> @test_minimumnum_f32x4(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_minimumnum_f32x4:
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; CHECK: .functype test_minimumnum_f32x4 (v128, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: local.get 1
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; CHECK-NEXT: f32x4.relaxed_min
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; CHECK-NEXT: # fallthrough-return
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%result = call <4 x float> @llvm.minimumnum.v4f32(<4 x float> %a, <4 x float> %b)
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ret <4 x float> %result
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}
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define <2 x double> @test_minnum_f64x2(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: test_minnum_f64x2:
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; CHECK: .functype test_minnum_f64x2 (v128, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: local.get 1
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; CHECK-NEXT: f64x2.relaxed_min
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; CHECK-NEXT: # fallthrough-return
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%result = call <2 x double> @llvm.minnum.v2f64(<2 x double> %a, <2 x double> %b)
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ret <2 x double> %result
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}
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define <2 x double> @test_minimumnum_f64x2(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: test_minimumnum_f64x2:
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; CHECK: .functype test_minimumnum_f64x2 (v128, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: local.get 1
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; CHECK-NEXT: f64x2.relaxed_min
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; CHECK-NEXT: # fallthrough-return
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%result = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> %a, <2 x double> %b)
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ret <2 x double> %result
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}
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declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>)
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declare <4 x float> @llvm.fminimumnum.v4f32(<4 x float>, <4 x float>)
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declare <2 x double> @llvm.minnum.v2f64(<2 x double>, <2 x double>)
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declare <2 x double> @llvm.fminimumnum.v2f64(<2 x double>, <2 x double>)

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