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pussuwAlan C. Assis
pussuw
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Alan C. Assis
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mpfs/mpfs_rcc: Add stub driver for FPGA clock and reset controller
This patch adds a driver framework to control individual FPGA reset and clock gates. For FPGA devices, only the fabric (FIC0/FIC1/FIC3) clock and reset can be controlled, which affects the whole fabric / domain. This is problematic for obvious reasons. For MSS peripherals, clocks and reset are controlled individually for each peripheral via MSS memory mapped registers (MPFS_SYSREG). To get the same capability for FPGA peripherals, the same controller needs to be fabricated on the FPGA. However, the FPGA clock/reset controller is entirely user dependent, so a generic implementation is not possible. However, a generic driver is needed in order to build the current FPGA peripheral drivers. A stub implementation of the driver is provided in order to achieve this. Signed-off-by: Ville Juven <ville.juven@unikie.com>
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‎arch/risc-v/src/mpfs/Kconfig‎

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@@ -828,6 +828,12 @@ config MPFS_MPUCFG
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---help---
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Enable driver to set MPUCFG entries.
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config MPFS_RCC
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bool "Enable Reset and Clock Controller (RCC) driver"
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default y
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---help---
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Enable driver for reset / clock controller.
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831837
config MPFS_HAVE_CORERMII
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bool "CoreRMII FPGA IP block configured"
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default n

‎arch/risc-v/src/mpfs/Make.defs‎

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@@ -122,3 +122,6 @@ ifeq ($(CONFIG_MPFS_MPUCFG),y)
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CHIP_CSRCS += mpfs_mpu.c
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endif
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ifeq ($(CONFIG_MPFS_RCC),y)
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CHIP_CSRCS += mpfs_rcc.c
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endif

‎arch/risc-v/src/mpfs/hardware/mpfs_sysreg.h‎

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@@ -137,6 +137,11 @@
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#define MPFS_SYSREG_SPARE_PERIM_RW_OFFSET 0x02DC /* Spare signal back to G5C */
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#define MPFS_SYSREG_SPARE_FIC_OFFSET 0x02E0 /* Unused FIC resets */
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#define MPFS_SYSREG_SOFT_RESET_CR (MPFS_SYSREG_BASE + \
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MPFS_SYSREG_SOFT_RESET_CR_OFFSET)
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#define MPFS_SYSREG_SUBBLK_CLOCK_CR (MPFS_SYSREG_BASE + \
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MPFS_SYSREG_SUBBLK_CLOCK_CR_OFFSET)
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140145
/* Register bit field definitions *******************************************/
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/* CLOCK_CONFIG_CR:

‎arch/risc-v/src/mpfs/mpfs_corepwm.c‎

Lines changed: 25 additions & 1 deletion
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@@ -44,7 +44,11 @@
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#include <arch/board/board.h>
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#include "mpfs_rcc.h"
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#include "hardware/mpfs_memorymap.h"
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#include "hardware/mpfs_corepwm.h"
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#include "hardware/mpfs_sysreg.h"
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#include "riscv_internal.h"
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/****************************************************************************
@@ -752,6 +756,25 @@ static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd,
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return -ENOTTY;
753757
}
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static int pwm_init(struct mpfs_pwmtimer_s *priv)
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{
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/* Toggle peripheral reset */
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mpfs_set_reset(MPFS_RCC_I2C, priv->pwmid, 1);
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mpfs_set_reset(MPFS_RCC_I2C, priv->pwmid, 0);
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/* Release FIC reset and enable clocks */
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modifyreg32(MPFS_SYSREG_SOFT_RESET_CR,
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SYSREG_SOFT_RESET_CR_FIC3 | SYSREG_SOFT_RESET_CR_FPGA,
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0);
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modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0,
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SYSREG_SUBBLK_CLOCK_CR_FIC3);
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
@@ -795,6 +818,7 @@ struct pwm_lowerhalf_s *mpfs_corepwm_init(int pwmid)
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return NULL;
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}
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pwm_init(lower);
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return (struct pwm_lowerhalf_s *)lower;
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}
800-

‎arch/risc-v/src/mpfs/mpfs_corespi.c‎

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Original file line numberDiff line numberDiff line change
@@ -44,6 +44,7 @@
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#include "mpfs_gpio.h"
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#include "mpfs_corespi.h"
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#include "mpfs_rcc.h"
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#include "hardware/mpfs_corespi.h"
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#include "hardware/mpfs_sysreg.h"
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#include "riscv_internal.h"
@@ -1513,6 +1514,11 @@ static void mpfs_spi_init(struct spi_dev_s *dev)
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15141515
up_disable_irq(priv->plic_irq);
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/* Toggle peripheral reset */
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mpfs_set_reset(MPFS_RCC_SPI, priv->id, 1);
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mpfs_set_reset(MPFS_RCC_SPI, priv->id, 0);
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/* Release FIC reset and enable clocks */
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modifyreg32(MPFS_SYSREG_SOFT_RESET_CR,

‎arch/risc-v/src/mpfs/mpfs_i2c.c‎

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Original file line numberDiff line numberDiff line change
@@ -48,6 +48,7 @@
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#include "mpfs_gpio.h"
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#include "mpfs_i2c.h"
51+
#include "mpfs_rcc.h"
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#include "riscv_internal.h"
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#include "hardware/mpfs_i2c.h"
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@@ -369,6 +370,11 @@ static int mpfs_i2c_init(struct mpfs_i2c_priv_s *priv)
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370371
if (priv->fpga)
371372
{
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/* Toggle peripheral reset */
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mpfs_set_reset(MPFS_RCC_I2C, priv->id, 1);
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mpfs_set_reset(MPFS_RCC_I2C, priv->id, 0);
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372378
/* FIC3 is used by many, don't reset it here, or many
373379
* FPGA based modules will stop working right here. Just
374380
* bring out of reset instead.

‎arch/risc-v/src/mpfs/mpfs_rcc.c‎

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@@ -0,0 +1,99 @@
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/****************************************************************************
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* arch/risc-v/src/mpfs/mpfs_rcc.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/spinlock.h>
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#include <errno.h>
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#include <sys/types.h>
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#include "mpfs_rcc.h"
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#include "mpfs_memorymap.h"
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#include "riscv_internal.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: mpfs_set_reset
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*
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* Description:
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* Enable / disable peripheral reset.
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*
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* Input Parameters:
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* rcc_id - Device id.
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* instance - Optional instance number for device.
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*
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* Returned Value:
70+
* Zero (OK) is returned on success; a negated errno value is returned on
71+
* any failure.
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*
73+
****************************************************************************/
74+
75+
int mpfs_set_reset(int rcc_id, int instance, bool state)
76+
{
77+
return -ENODEV;
78+
}
79+
80+
/****************************************************************************
81+
* Name: mpfs_set_clock
82+
*
83+
* Description:
84+
* Enable / disable peripheral clock.
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*
86+
* Input Parameters:
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* rcc_id - Device id.
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* instance - Optional instance number for device.
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*
90+
* Returned Value:
91+
* Zero (OK) is returned on success; a negated errno value is returned on
92+
* any failure.
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*
94+
****************************************************************************/
95+
96+
int mpfs_set_clock(int rcc_id, int instance, bool state)
97+
{
98+
return -ENODEV;
99+
}

‎arch/risc-v/src/mpfs/mpfs_rcc.h‎

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@@ -0,0 +1,121 @@
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/****************************************************************************
2+
* arch/risc-v/src/mpfs/mpfs_rcc.h
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*
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* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Licensed to the Apache Software Foundation (ASF) under one or more
7+
* contributor license agreements. See the NOTICE file distributed with
8+
* this work for additional information regarding copyright ownership. The
9+
* ASF licenses this file to you under the Apache License, Version 2.0 (the
10+
* "License"); you may not use this file except in compliance with the
11+
* License. You may obtain a copy of the License at
12+
*
13+
* http://www.apache.org/licenses/LICENSE-2.0
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*
15+
* Unless required by applicable law or agreed to in writing, software
16+
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
17+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
18+
* License for the specific language governing permissions and limitations
19+
* under the License.
20+
*
21+
****************************************************************************/
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23+
#ifndef ARCH_RISC_V_SRC_MPFS_MPFS_RCC_H
24+
#define ARCH_RISC_V_SRC_MPFS_MPFS_RCC_H
25+
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/****************************************************************************
27+
* Included Files
28+
****************************************************************************/
29+
30+
#include <nuttx/config.h>
31+
32+
#include <stdint.h>
33+
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/****************************************************************************
35+
* Pre-processor Definitions
36+
****************************************************************************/
37+
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/****************************************************************************
39+
* Public Types
40+
****************************************************************************/
41+
42+
enum mpfs_rcc_id_e
43+
{
44+
MPFS_RCC_CAN,
45+
MPFS_RCC_I2C,
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MPFS_RCC_PWM,
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MPFS_RCC_SPI,
48+
MPFS_RCC_UART,
49+
MPFS_RCC_LAST,
50+
};
51+
52+
#ifndef __ASSEMBLY__
53+
54+
/****************************************************************************
55+
* Public Data
56+
****************************************************************************/
57+
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#undef EXTERN
59+
#if defined(__cplusplus)
60+
#define EXTERN extern "C"
61+
extern "C"
62+
{
63+
#else
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#define EXTERN extern
65+
#endif
66+
67+
/****************************************************************************
68+
* Public Function Prototypes
69+
****************************************************************************/
70+
71+
/****************************************************************************
72+
* Name: mpfs_set_reset
73+
*
74+
* Description:
75+
* Enable / disable peripheral reset.
76+
*
77+
* Input Parameters:
78+
* rcc_id - Device id.
79+
* instance - Optional instance number for device.
80+
*
81+
* Returned Value:
82+
* Zero (OK) is returned on success; a negated errno value is returned on
83+
* any failure.
84+
*
85+
****************************************************************************/
86+
87+
#ifdef CONFIG_MPFS_RCC
88+
int mpfs_set_reset(int rcc_id, int instance, bool state);
89+
#else
90+
# define mpfs_set_reset(rcc_id, instance, state) (0)
91+
#endif
92+
93+
/****************************************************************************
94+
* Name: mpfs_set_clock
95+
*
96+
* Description:
97+
* Enable / disable peripheral clock.
98+
*
99+
* Input Parameters:
100+
* rcc_id - Device id.
101+
* instance - Optional instance number for device.
102+
*
103+
* Returned Value:
104+
* Zero (OK) is returned on success; a negated errno value is returned on
105+
* any failure.
106+
*
107+
****************************************************************************/
108+
109+
#ifdef CONFIG_MPFS_RCC
110+
int mpfs_set_clock(int rcc_id, int instance, bool state);
111+
#else
112+
# define mpfs_set_clock(rcc_id, instance, state) (0)
113+
#endif
114+
115+
#if defined(__cplusplus)
116+
}
117+
#endif
118+
#undef EXTERN
119+
120+
#endif /* __ASSEMBLY__ */
121+
#endif /* ARCH_RISC_V_SRC_MPFS_MPFS_RCC_H */

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