Skip to content

Commit 8b68921

Browse files
jerenkrantzjerenkrantz
committed
risc-v/litex: Add 64-bit S-mode vexiiriscv support for litex.
Most of the peripheral support matches litex vexriscv-smp. * arch/risc-v/Kconfig: Defer RV32 selection to core as litex board can do RV64. * arch/risc-v/src/litex/Make.defs arch/risc-v/src/litex/hardware/litex_clint.h arch/risc-v/src/litex/hardware/litex_memorymap.h arch/risc-v/src/litex/hardware/litex_plic.h arch/risc-v/src/litex/litex_irq.c arch/risc-v/src/litex/litex_irq_dispatch.c: Add CONFIG_LITEX_CORE_VEXIIRISCV conditional where vexriscv_smp conditionals are. * boards/risc-v/litex/arty_a7/configs/nsh-vexii/defconfig: New config. * boards/risc-v/litex/arty_a7/include/vexii_irq.h: vexiiriscv irq defintion. * boards/risc-v/litex/arty_a7/include/vexii_memorymap.h: vexiiriscv memory map. * boards/risc-v/litex/arty_a7/scripts/ld.script: Define __global_pointer for toolchain happiness matching other RISC-V linker scripts. (This commit was written with assistance from Claude Code.) Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
1 parent 19dcd45 commit 8b68921

File tree

11 files changed

+231
-11
lines changed

11 files changed

+231
-11
lines changed

‎arch/risc-v/Kconfig‎

Lines changed: 19 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,6 @@ config ARCH_CHIP_K210
4444

4545
config ARCH_CHIP_LITEX
4646
bool "Enjoy Digital LITEX VEXRISCV"
47-
select ARCH_RV32
4847
select ARCH_RV_ISA_M
4948
select ARCH_RV_ISA_A
5049
select ARCH_DCACHE
@@ -53,7 +52,7 @@ config ARCH_CHIP_LITEX
5352
select LIBC_FDT
5453
select DEVICE_TREE
5554
---help---
56-
Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA).
55+
Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA or RV64GC).
5756

5857
config ARCH_CHIP_BL602
5958
bool "BouffaloLab BL602"
@@ -783,9 +782,11 @@ choice
783782

784783
config LITEX_CORE_VEXRISCV
785784
bool "vexriscv core"
785+
select ARCH_RV32
786786

787787
config LITEX_CORE_VEXRISCV_SMP
788788
bool "vexriscv_smp core"
789+
select ARCH_RV32
789790
select ARCH_HAVE_MPU
790791
select ARCH_RV_ISA_C
791792
select ARCH_MMU_TYPE_SV32
@@ -795,6 +796,22 @@ config LITEX_CORE_VEXRISCV_SMP
795796
select ARCH_HAVE_ELF_EXECUTABLE
796797
select ARCH_HAVE_PERF_EVENTS
797798

799+
config LITEX_CORE_VEXIIRISCV
800+
bool "vexiiriscv core"
801+
select ARCH_RV64
802+
select ARCH_RV_ISA_M
803+
select ARCH_RV_ISA_A
804+
select ARCH_RV_ISA_C
805+
select ARCH_HAVE_FPU
806+
select ARCH_HAVE_DPFPU
807+
select ARCH_HAVE_MPU
808+
select ARCH_MMU_TYPE_SV39
809+
select ARCH_HAVE_ADDRENV
810+
select ARCH_NEED_ADDRENV_MAPPING
811+
select ARCH_HAVE_S_MODE
812+
select ARCH_HAVE_ELF_EXECUTABLE
813+
select ARCH_HAVE_PERF_EVENTS
814+
798815
endchoice # LITEX Core Selection
799816

800817
endif # ARCH_CHIP_LITEX

‎arch/risc-v/src/litex/Make.defs‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,8 @@ include common/Make.defs
2626
# the first object file, so it will appear at address 0
2727
ifeq ($(CONFIG_LITEX_CORE_VEXRISCV_SMP),y)
2828
HEAD_ASRC = litex_shead.S
29+
else ifeq ($(CONFIG_LITEX_CORE_VEXIIRISCV),y)
30+
HEAD_ASRC = litex_shead.S
2931
else
3032
HEAD_ASRC = litex_head.S
3133
endif

‎arch/risc-v/src/litex/hardware/litex_clint.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626
/****************************************************************************
2727
* Pre-processor Definitions
2828
****************************************************************************/
29-
#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
29+
#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV)
3030

3131
#define LITEX_CLINT_MSIP (LITEX_CLINT_BASE + 0x0000)
3232
#define LITEX_CLINT_MTIMECMP (LITEX_CLINT_BASE + 0x4000)
@@ -38,6 +38,6 @@
3838
#define LITEX_CLINT_MTIME (LITEX_CPUTIMER_BASE + 0x04)
3939
#define LITEX_CLINT_MTIMECMP (LITEX_CPUTIMER_BASE + 0x0C)
4040

41-
#endif /* CONFIG_LITEX_CORE_VEXRISCV_SMP */
41+
#endif /* CONFIG_LITEX_CORE_VEXRISCV_SMP || CONFIG_LITEX_CORE_VEXIIRISCV */
4242

4343
#endif /* __ARCH_RISCV_SRC_LITEX_HARDWARE_LITEX_CLINT_H */

‎arch/risc-v/src/litex/hardware/litex_memorymap.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@
3737

3838
/* Register Base Address ****************************************************/
3939

40-
#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
40+
#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV)
4141
#define LITEX_CLINT_BASE 0xf0010000
4242
#define LITEX_PLIC_BASE 0xf0c00000
4343
#define LITEX_ETHMAC_BASE 0xf0002000

‎arch/risc-v/src/litex/hardware/litex_plic.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@
3333
* Pre-processor Definitions
3434
****************************************************************************/
3535

36-
#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
36+
#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV)
3737
# define LITEX_PLIC_PRIORITY (LITEX_PLIC_BASE + 0x000000)
3838
# define LITEX_PLIC_PENDING1 (LITEX_PLIC_BASE + 0x001000)
3939

‎arch/risc-v/src/litex/litex_irq.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -68,8 +68,8 @@ void up_irqinitialize(void)
6868

6969
/* litex vexriscv dont have priority and threshold control */
7070

71-
#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
72-
/* litex vexriscv_smp does. */
71+
#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV)
72+
/* litex vexriscv_smp and vexiiriscv do. */
7373

7474
/* Set priority for all global interrupts to 1 (lowest) */
7575

@@ -106,7 +106,7 @@ void up_irqinitialize(void)
106106
*
107107
****************************************************************************/
108108

109-
#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
109+
#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV)
110110
void up_disable_irq(int irq)
111111
{
112112
int extirq;
@@ -187,7 +187,7 @@ void up_disable_irq(int irq)
187187
*
188188
****************************************************************************/
189189

190-
#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
190+
#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV)
191191
void up_enable_irq(int irq)
192192
{
193193
int extirq;

‎arch/risc-v/src/litex/litex_irq_dispatch.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@
4949
* riscv_dispatch_irq
5050
****************************************************************************/
5151

52-
#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
52+
#if defined(CONFIG_LITEX_CORE_VEXRISCV_SMP) || defined(CONFIG_LITEX_CORE_VEXIIRISCV)
5353
void *riscv_dispatch_irq(uintptr_t vector, uintreg_t *regs)
5454
{
5555
int irq = (vector & 0x3f);

‎boards/risc-v/litex/arty_a7/configs/nsh-vexii/defconfig‎

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
1+
#
2+
# This file is autogenerated: PLEASE DO NOT EDIT IT.
3+
#
4+
# You can use "make menuconfig" to make any modifications to the installed .config file.
5+
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
6+
# modifications.
7+
#
8+
# CONFIG_DISABLE_PTHREAD is not set
9+
# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set
10+
# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set
11+
# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set
12+
# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set
13+
# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set
14+
# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set
15+
# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set
16+
# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set
17+
# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set
18+
# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set
19+
# CONFIG_NSH_DISABLEBG is not set
20+
# CONFIG_NSH_DISABLE_LOSMART is not set
21+
# CONFIG_NSH_DISABLE_UNAME is not set
22+
# CONFIG_STANDARD_SERIAL is not set
23+
CONFIG_ARCH="risc-v"
24+
CONFIG_ARCH_BOARD="arty_a7"
25+
CONFIG_ARCH_BOARD_ARTY_A7=y
26+
CONFIG_ARCH_CHIP="litex"
27+
CONFIG_ARCH_CHIP_LITEX=y
28+
CONFIG_ARCH_INTERRUPTSTACK=8192
29+
CONFIG_ARCH_RISCV=y
30+
CONFIG_ARCH_STACKDUMP=y
31+
CONFIG_ARCH_USE_S_MODE=y
32+
CONFIG_BOARDCTL_RESET=y
33+
CONFIG_BOARD_LOOPSPERMSEC=10000
34+
CONFIG_BUILTIN=y
35+
CONFIG_DEBUG_FULLOPT=y
36+
CONFIG_DEBUG_SYMBOLS=y
37+
CONFIG_DEFAULT_SMALL=y
38+
CONFIG_DEV_ZERO=y
39+
CONFIG_EXAMPLES_HELLO=y
40+
CONFIG_EXAMPLES_HELLO_STACKSIZE=8192
41+
CONFIG_FS_PROCFS=y
42+
CONFIG_IDLETHREAD_STACKSIZE=8192
43+
CONFIG_INIT_ENTRYPOINT="nsh_main"
44+
CONFIG_INIT_STACKSIZE=8192
45+
CONFIG_INTELHEX_BINARY=y
46+
CONFIG_LIBC_PERROR_STDOUT=y
47+
CONFIG_LIBC_STRERROR=y
48+
CONFIG_LITEX_CORE_VEXIIRISCV=y
49+
CONFIG_LITEX_CUSTOM_IRQ_DEFINITIONS_PATH="../../../../boards/risc-v/litex/arty_a7/include/vexii_irq.h"
50+
CONFIG_LITEX_CUSTOM_MEMORY_MAP_PATH="../../../../boards/risc-v/litex/arty_a7/include/vexii_memorymap.h"
51+
CONFIG_LITEX_USE_CUSTOM_IRQ_DEFINITIONS=y
52+
CONFIG_LITEX_USE_CUSTOM_MEMORY_MAP=y
53+
CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
54+
CONFIG_NSH_ARCHINIT=y
55+
CONFIG_NSH_BUILTIN_APPS=y
56+
CONFIG_NSH_FILEIOSIZE=64
57+
CONFIG_NSH_STRERROR=y
58+
CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=8192
59+
CONFIG_PTHREAD_STACK_DEFAULT=8192
60+
CONFIG_RAM_SIZE=268435456
61+
CONFIG_RAM_START=0x40000000
62+
CONFIG_RAW_BINARY=y
63+
CONFIG_RR_INTERVAL=200
64+
CONFIG_SCHED_WAITPID=y
65+
CONFIG_STACK_COLORATION=y
66+
CONFIG_START_DAY=20
67+
CONFIG_START_MONTH=3
68+
CONFIG_START_YEAR=2020
69+
CONFIG_SYSTEM_NSH=y
70+
CONFIG_TASK_NAME_SIZE=12
71+
CONFIG_TESTING_GETPRIME=y
72+
CONFIG_UART0_RXBUFSIZE=128
73+
CONFIG_UART0_SERIAL_CONSOLE=y
74+
CONFIG_UART0_TXBUFSIZE=128

‎boards/risc-v/litex/arty_a7/include/vexii_irq.h‎

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
/****************************************************************************
2+
* boards/risc-v/litex/arty_a7/include/vexii_irq.h
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Licensed to the Apache Software Foundation (ASF) under one or more
7+
* contributor license agreements. See the NOTICE file distributed with
8+
* this work for additional information regarding copyright ownership. The
9+
* ASF licenses this file to you under the Apache License, Version 2.0 (the
10+
* "License"); you may not use this file except in compliance with the
11+
* License. You may obtain a copy of the License at
12+
*
13+
* http://www.apache.org/licenses/LICENSE-2.0
14+
*
15+
* Unless required by applicable law or agreed to in writing, software
16+
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
17+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
18+
* License for the specific language governing permissions and limitations
19+
* under the License.
20+
*
21+
* Auto-generated: 2025-12-28 11:16:55
22+
* Source: LiteX soc.h
23+
*
24+
****************************************************************************/
25+
26+
#ifndef __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_IRQ_H
27+
#define __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_IRQ_H
28+
29+
/****************************************************************************
30+
* Included Files
31+
****************************************************************************/
32+
33+
#include <arch/mode.h>
34+
35+
/****************************************************************************
36+
* Pre-processor Definitions
37+
****************************************************************************/
38+
39+
/* Custom IRQ definitions for LiteX VexiiRISCV core */
40+
41+
/* Map RISC-V external IRQs to NuttX IRQ numbers */
42+
43+
#define LITEX_IRQ_UART0 (RISCV_IRQ_EXT + 1)
44+
#define LITEX_IRQ_TIMER0 (RISCV_IRQ_EXT + 2)
45+
#define LITEX_IRQ_ETHMAC (RISCV_IRQ_EXT + 3)
46+
#define LITEX_IRQ_GPIO_BASE (RISCV_IRQ_EXT + 4)
47+
#define LITEX_IRQ_GPIO_LENGTH 8
48+
49+
/* The last hardware IRQ number */
50+
51+
#define LITEX_IRQ_LAST (LITEX_IRQ_GPIO_BASE + LITEX_IRQ_GPIO_LENGTH)
52+
53+
/* Second level GPIO interrupts if enabled */
54+
55+
#ifdef CONFIG_LITEX_GPIO_IRQ
56+
# define LITEX_NIRQ_GPIO (LITEX_IRQ_GPIO_LENGTH * 32)
57+
# define LITEX_FIRST_GPIOIRQ (LITEX_IRQ_LAST + 1)
58+
# define LITEX_LAST_GPIOIRQ (LITEX_FIRST_GPIOIRQ + LITEX_NIRQ_GPIO)
59+
#else
60+
# define LITEX_NIRQ_GPIO 0
61+
#endif
62+
63+
/* Total number of IRQs */
64+
65+
#define NR_IRQS (LITEX_IRQ_LAST + LITEX_NIRQ_GPIO + 1)
66+
67+
#endif /* __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_IRQ_H */

‎boards/risc-v/litex/arty_a7/include/vexii_memorymap.h‎

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
1+
/****************************************************************************
2+
* boards/risc-v/litex/arty_a7/include/vexii_memorymap.h
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Licensed to the Apache Software Foundation (ASF) under one or more
7+
* contributor license agreements. See the NOTICE file distributed with
8+
* this work for additional information regarding copyright ownership. The
9+
* ASF licenses this file to you under the Apache License, Version 2.0 (the
10+
* "License"); you may not use this file except in compliance with the
11+
* License. You may obtain a copy of the License at
12+
*
13+
* http://www.apache.org/licenses/LICENSE-2.0
14+
*
15+
* Unless required by applicable law or agreed to in writing, software
16+
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
17+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
18+
* License for the specific language governing permissions and limitations
19+
* under the License.
20+
*
21+
* Auto-generated: 2025-12-28 11:16:55
22+
* Source: LiteX csr.h
23+
*
24+
****************************************************************************/
25+
26+
#ifndef __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_MEMORYMAP_H
27+
#define __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_MEMORYMAP_H
28+
29+
/****************************************************************************
30+
* Pre-processor Definitions
31+
****************************************************************************/
32+
33+
/* Custom memory map for LiteX VexiiRISCV core */
34+
35+
/* Core Peripherals */
36+
37+
#define LITEX_CLINT_BASE 0xf0010000UL
38+
#define LITEX_PLIC_BASE 0xf0c00000UL
39+
40+
/* SOC Peripherals */
41+
42+
#define LITEX_UART0_BASE 0xf0001000UL
43+
#define LITEX_TIMER0_BASE 0xf0001800UL
44+
45+
/* Ethernet (if enabled) */
46+
47+
#define LITEX_ETHMAC_BASE 0xf0002000UL
48+
#define LITEX_ETHPHY_BASE 0xf0002800UL
49+
50+
/* Other Peripherals */
51+
52+
#define LITEX_CTRL_BASE 0xf0000000UL
53+
#define LITEX_DDRPHY_BASE 0xf0000800UL
54+
#define LITEX_IDENTIFIER_MEM_BASE 0xf0003000UL
55+
#define LITEX_LEDS_BASE 0xf0003800UL
56+
#define LITEX_SDRAM_BASE 0xf0004000UL
57+
58+
#endif /* __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_VEXII_MEMORYMAP_H */

0 commit comments

Comments
 (0)