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dstric-aqueductdstric-aqueduct
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fix to add Can to ccm mod
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‎imxrt-hal/src/ccm.rs‎

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@@ -965,3 +965,162 @@ pub mod spi {
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}
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}
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}
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/// Timing configurations for FlexCAN peripherals
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pub mod can {
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use super::{ral::ccm, Divider, Frequency};
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#[derive(Clone, Copy)]
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#[non_exhaustive] // Not all variants added
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pub enum ClockSelect {
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Pll2,
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}
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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#[allow(non_camel_case_types)] // Easier mapping if the names are consistent
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#[repr(u32)]
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pub enum PrescalarSelect {
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/// 0b000000: Divide by 1
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DIVIDE_1 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_1,
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/// 0b000001: Divide by 2
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DIVIDE_2 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_2,
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/// 0b000010: Divide by 3
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DIVIDE_3 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_3,
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/// 0b000011: Divide by 4
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DIVIDE_4 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_4,
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/// 0b000100: Divide by 5
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DIVIDE_5 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_5,
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/// 0b000101: Divide by 6
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DIVIDE_6 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_6,
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/// 0b000110: Divide by 7
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DIVIDE_7 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_7,
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/// 0b000111: Divide by 8
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DIVIDE_8 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_8,
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/// 0b001000: Divide by 9
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DIVIDE_9 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_9,
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/// 0b001001: Divide by 10
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DIVIDE_10 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_10,
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/// 0b001010: Divide by 11
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DIVIDE_11 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_11,
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/// 0b001011: Divide by 12
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DIVIDE_12 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_12,
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/// 0b001100: Divide by 13
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DIVIDE_13 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_13,
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/// 0b001101: Divide by 14
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DIVIDE_14 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_14,
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/// 0b001110: Divide by 15
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DIVIDE_15 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_15,
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/// 0b001111: Divide by 16
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DIVIDE_16 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_16,
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/// 0b010000: Divide by 17
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DIVIDE_17 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_17,
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/// 0b010001: Divide by 18
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DIVIDE_18 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_18,
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/// 0b010010: Divide by 19
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DIVIDE_19 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_19,
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/// 0b010011: Divide by 20
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DIVIDE_20 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_20,
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/// 0b010100: Divide by 21
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DIVIDE_21 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_21,
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/// 0b010101: Divide by 22
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DIVIDE_22 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_22,
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/// 0b010110: Divide by 23
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DIVIDE_23 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_23,
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/// 0b010111: Divide by 24
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DIVIDE_24 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_24,
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/// 0b011000: Divide by 25
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DIVIDE_25 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_25,
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/// 0b011001: Divide by 26
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DIVIDE_26 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_26,
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/// 0b011010: Divide by 27
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DIVIDE_27 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_27,
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/// 0b011011: Divide by 28
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DIVIDE_28 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_28,
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/// 0b011100: Divide by 29
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DIVIDE_29 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_29,
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/// 0b011101: Divide by 30
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DIVIDE_30 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_30,
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/// 0b011110: Divide by 31
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DIVIDE_31 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_31,
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/// 0b011111: Divide by 32
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DIVIDE_32 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_32,
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/// 0b100000: Divide by 33
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DIVIDE_33 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_33,
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/// 0b100001: Divide by 34
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DIVIDE_34 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_34,
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/// 0b100010: Divide by 35
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DIVIDE_35 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_35,
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/// 0b100011: Divide by 36
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DIVIDE_36 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_36,
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/// 0b100100: Divide by 37
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DIVIDE_37 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_37,
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/// 0b100101: Divide by 38
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DIVIDE_38 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_38,
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/// 0b100110: Divide by 39
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DIVIDE_39 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_39,
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/// 0b100111: Divide by 40
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DIVIDE_40 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_40,
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/// 0b101000: Divide by 41
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DIVIDE_41 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_41,
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/// 0b101001: Divide by 42
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DIVIDE_42 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_42,
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/// 0b101010: Divide by 43
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DIVIDE_43 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_43,
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/// 0b101011: Divide by 44
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DIVIDE_44 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_44,
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/// 0b101100: Divide by 45
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DIVIDE_45 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_45,
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/// 0b101101: Divide by 46
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DIVIDE_46 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_46,
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/// 0b101110: Divide by 47
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DIVIDE_47 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_47,
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/// 0b101111: Divide by 48
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DIVIDE_48 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_48,
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/// 0b110000: Divide by 49
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DIVIDE_49 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_49,
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/// 0b110001: Divide by 50
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DIVIDE_50 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_50,
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/// 0b110010: Divide by 51
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DIVIDE_51 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_51,
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/// 0b110011: Divide by 52
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DIVIDE_52 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_52,
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/// 0b110100: Divide by 53
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DIVIDE_53 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_53,
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/// 0b110101: Divide by 54
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DIVIDE_54 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_54,
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/// 0b110110: Divide by 55
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DIVIDE_55 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_55,
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/// 0b110111: Divide by 56
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DIVIDE_56 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_56,
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/// 0b111000: Divide by 57
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DIVIDE_57 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_57,
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/// 0b111001: Divide by 58
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DIVIDE_58 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_58,
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/// 0b111010: Divide by 59
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DIVIDE_59 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_59,
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/// 0b111011: Divide by 60
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DIVIDE_60 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_60,
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/// 0b111100: Divide by 61
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DIVIDE_61 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_61,
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/// 0b111101: Divide by 62
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DIVIDE_62 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_62,
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/// 0b111110: Divide by 63
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DIVIDE_63 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_63,
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/// 0b111111: Divide by 64
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DIVIDE_64 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_64,
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}
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impl From<ClockSelect> for Frequency {
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fn from(clock_select: ClockSelect) -> Self {
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match clock_select {
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ClockSelect::Pll2 => Frequency(528_000_000),
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}
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}
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}
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impl From<PrescalarSelect> for Divider {
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fn from(prescalar_select: PrescalarSelect) -> Self {
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Divider((prescalar_select as u32) + 1)
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}
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}
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}

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