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‎CONTRIBUTING.md‎

Lines changed: 32 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
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Thanks for helping us build embedded Rust support for NXP's i.MX RT processors! Please open an issue if
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5-
- you find a bug in any chip HAL
5+
- you find a bug in the HAL, RAL, or IOMUXC crates
66
- you have an idea for a feature
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- something isn't clear in our documentation
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@@ -20,22 +20,45 @@ You'll need
2020
```bash
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rustup target add thumbv7em-none-eabihf
2222
```
23-
### Chip-specific HAL(s)
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25-
We support one HAL crate per i.MX RT processor family. A "processor family" is described by an NXP datasheet and reference manual. For example, the `imxrt1060-hal` supports the [i.MX RT1060 Crossover Processors](https://www.nxp.com/docs/en/nxp/data-sheets/IMXRT1060CEC.pdf), which includes the following processors:
24+
### RAL
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27-
- i.MX RT 1061
28-
- i.MX RT 1062
26+
The `imxrt-ral` crate is auto-generated from the checked-in SVD files, available in `imxrt-ral/svd`. It's checked into git, and you should always have whatever represents the latest auto-generated RAL. Generally, you should **not** manually change RAL source files; rather, you should describe changes in `imxrtral.py`, the Python script that auto-generates the RAL.
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30-
When developing the HAL(s) a quick way to check everything compiles, in the project root
28+
To generate the RAL,
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30+
- Install Python 3. You'll need at least Python 3.6.
31+
- Install the Python dependencies needed to generate the RAL: `pip3 install --user svdtools`. Alternatively, use the rules in the RAL's `Makefile` to create a virtual environment with the necessary dependencies: `make venv update-venv && source venv/bin/activate`.
32+
- Run `make` in the `imxrt-ral` directory: `make -C imxrt-ral`. The auto-generation script might generate warnings; that's OK.
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34+
If everything went well, you should find that the `imxrt-ral/src` directory is populated with Rust files. If you made changes in `imxrtral.py`, you should see those changes reflected in the Rust files. The RAL can build by itself: `cd imxrt-ral && cargo check --features imxrt1062 --target thumbv7em-none-eabihf`.
35+
36+
If you add a SVD patch, or if you change something in `imxrtral.py`, you'll need to re-generate the RAL to realize the change.
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38+
### HAL
39+
40+
Make sure you've generated the RAL (see above). When developing the HAL, specify a feature flag from the command line. To check the HAL for `imxrt1062` processors, `cd imxrt-hal`, then
41+
42+
```
43+
cargo check --features imxrt1062 --target thumbv7em-none-eabihf
3244
```
33-
cargo check --target thumbv7em-none-eabihf
45+
46+
### IOMUXC
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48+
The `imxrt-iomuxc` crate family does not require any feature flags, and it will build for your host. Consider using `--package` flags to build and test the crate family in one command:
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3450
```
51+
cargo build --package=imxrt-iomuxc --package=imxrt-iomuxc-build
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cargo test -p imxrt-iomuxc -p imxrt-iomuxc-build
53+
```
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55+
### SVD Patches
56+
57+
To modify the RAL, you'll need to describe your change as an SVD patch. If you'd like to add patches to the i.MX RT SVD files, learn about [svdtools](https://github.com/stm32-rs/svdtools). Use some of the existing SVD patches as a guide.
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3659
### Testing
3760

38-
Our CI system ensures that the RAL and HAL(s) build for all processor variants. But, we can't automatically test against hardware! To test your changes on hardware, you'll need to test the RAL and the HAL(s) using another project, like a Rust BSP crate. Some BSP crates that use the `imxrt1060-hal` include
61+
Our CI system ensures that the RAL and HAL builds for all processor variants. But, we can't automatically test against hardware! To test your changes on hardware, you'll need to test the RAL and the HAL using another project, like a Rust BSP crate. Some BSP crates that use the `imxrt-hal` include
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4063
- [the `imxrt1060evk-bsp` crate](https://github.com/imxrt-rs/imxrt1060evk-bsp)
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- [the `teensy4-bsp` crate](https://github.com/mciantyre/teensy4-rs)
@@ -53,4 +76,4 @@ Follow the instructions in those projects to prepare an environment for testing
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## Release Steps
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56-
To create a release of the RAL and HAL crates, see [RELEASE.md](docs/RELEASE.md).
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To create a release of the RAL and HAL crates, see [RELEASE.md](docs/RELEASE.md).

‎imxrt-hal/src/ccm.rs‎

Lines changed: 28 additions & 159 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,10 @@ impl PLL1 {
5757
PLL1(())
5858
}
5959

60+
#[cfg(any(feature = "imxrt1011", feature = "imxrt1015"))]
61+
pub const ARM_HZ: u32 = 500_000_000;
62+
63+
#[cfg(any(feature = "imxrt1064", feature = "imxrt1062", feature = "imxrt1061"))]
6064
pub const ARM_HZ: u32 = 600_000_000;
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6266
/// Set the clock speed for the ARM core. This represents the base processor frequency.
@@ -921,165 +925,30 @@ pub mod spi {
921925
LPSPI_PODF_6 = ccm::CBCMR::LPSPI_PODF::RW::LPSPI_PODF_6,
922926
/// 0b0111: divide by 8
923927
LPSPI_PODF_7 = ccm::CBCMR::LPSPI_PODF::RW::LPSPI_PODF_7,
924-
}
925-
926-
impl From<ClockSelect> for Frequency {
927-
fn from(clock_select: ClockSelect) -> Self {
928-
match clock_select {
929-
ClockSelect::Pll2 => Frequency(528_000_000),
930-
}
931-
}
932-
}
933-
934-
impl From<PrescalarSelect> for Divider {
935-
fn from(prescalar_select: PrescalarSelect) -> Self {
936-
Divider((prescalar_select as u32) + 1)
937-
}
938-
}
939-
}
940-
941-
/// Timing configurations for FlexCAN peripherals
942-
pub mod can {
943-
use super::{ral::ccm, Divider, Frequency};
944-
945-
#[derive(Clone, Copy)]
946-
#[non_exhaustive] // Not all variants added
947-
pub enum ClockSelect {
948-
Pll2,
949-
}
950-
951-
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
952-
#[allow(non_camel_case_types)] // Easier mapping if the names are consistent
953-
#[repr(u32)]
954-
pub enum PrescalarSelect {
955-
/// 0b000000: Divide by 1
956-
DIVIDE_1 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_1,
957-
/// 0b000001: Divide by 2
958-
DIVIDE_2 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_2,
959-
/// 0b000010: Divide by 3
960-
DIVIDE_3 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_3,
961-
/// 0b000011: Divide by 4
962-
DIVIDE_4 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_4,
963-
/// 0b000100: Divide by 5
964-
DIVIDE_5 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_5,
965-
/// 0b000101: Divide by 6
966-
DIVIDE_6 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_6,
967-
/// 0b000110: Divide by 7
968-
DIVIDE_7 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_7,
969-
/// 0b000111: Divide by 8
970-
DIVIDE_8 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_8,
971-
/// 0b001000: Divide by 9
972-
DIVIDE_9 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_9,
973-
/// 0b001001: Divide by 10
974-
DIVIDE_10 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_10,
975-
/// 0b001010: Divide by 11
976-
DIVIDE_11 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_11,
977-
/// 0b001011: Divide by 12
978-
DIVIDE_12 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_12,
979-
/// 0b001100: Divide by 13
980-
DIVIDE_13 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_13,
981-
/// 0b001101: Divide by 14
982-
DIVIDE_14 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_14,
983-
/// 0b001110: Divide by 15
984-
DIVIDE_15 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_15,
985-
/// 0b001111: Divide by 16
986-
DIVIDE_16 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_16,
987-
/// 0b010000: Divide by 17
988-
DIVIDE_17 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_17,
989-
/// 0b010001: Divide by 18
990-
DIVIDE_18 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_18,
991-
/// 0b010010: Divide by 19
992-
DIVIDE_19 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_19,
993-
/// 0b010011: Divide by 20
994-
DIVIDE_20 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_20,
995-
/// 0b010100: Divide by 21
996-
DIVIDE_21 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_21,
997-
/// 0b010101: Divide by 22
998-
DIVIDE_22 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_22,
999-
/// 0b010110: Divide by 23
1000-
DIVIDE_23 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_23,
1001-
/// 0b010111: Divide by 24
1002-
DIVIDE_24 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_24,
1003-
/// 0b011000: Divide by 25
1004-
DIVIDE_25 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_25,
1005-
/// 0b011001: Divide by 26
1006-
DIVIDE_26 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_26,
1007-
/// 0b011010: Divide by 27
1008-
DIVIDE_27 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_27,
1009-
/// 0b011011: Divide by 28
1010-
DIVIDE_28 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_28,
1011-
/// 0b011100: Divide by 29
1012-
DIVIDE_29 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_29,
1013-
/// 0b011101: Divide by 30
1014-
DIVIDE_30 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_30,
1015-
/// 0b011110: Divide by 31
1016-
DIVIDE_31 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_31,
1017-
/// 0b011111: Divide by 32
1018-
DIVIDE_32 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_32,
1019-
/// 0b100000: Divide by 33
1020-
DIVIDE_33 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_33,
1021-
/// 0b100001: Divide by 34
1022-
DIVIDE_34 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_34,
1023-
/// 0b100010: Divide by 35
1024-
DIVIDE_35 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_35,
1025-
/// 0b100011: Divide by 36
1026-
DIVIDE_36 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_36,
1027-
/// 0b100100: Divide by 37
1028-
DIVIDE_37 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_37,
1029-
/// 0b100101: Divide by 38
1030-
DIVIDE_38 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_38,
1031-
/// 0b100110: Divide by 39
1032-
DIVIDE_39 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_39,
1033-
/// 0b100111: Divide by 40
1034-
DIVIDE_40 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_40,
1035-
/// 0b101000: Divide by 41
1036-
DIVIDE_41 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_41,
1037-
/// 0b101001: Divide by 42
1038-
DIVIDE_42 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_42,
1039-
/// 0b101010: Divide by 43
1040-
DIVIDE_43 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_43,
1041-
/// 0b101011: Divide by 44
1042-
DIVIDE_44 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_44,
1043-
/// 0b101100: Divide by 45
1044-
DIVIDE_45 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_45,
1045-
/// 0b101101: Divide by 46
1046-
DIVIDE_46 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_46,
1047-
/// 0b101110: Divide by 47
1048-
DIVIDE_47 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_47,
1049-
/// 0b101111: Divide by 48
1050-
DIVIDE_48 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_48,
1051-
/// 0b110000: Divide by 49
1052-
DIVIDE_49 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_49,
1053-
/// 0b110001: Divide by 50
1054-
DIVIDE_50 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_50,
1055-
/// 0b110010: Divide by 51
1056-
DIVIDE_51 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_51,
1057-
/// 0b110011: Divide by 52
1058-
DIVIDE_52 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_52,
1059-
/// 0b110100: Divide by 53
1060-
DIVIDE_53 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_53,
1061-
/// 0b110101: Divide by 54
1062-
DIVIDE_54 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_54,
1063-
/// 0b110110: Divide by 55
1064-
DIVIDE_55 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_55,
1065-
/// 0b110111: Divide by 56
1066-
DIVIDE_56 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_56,
1067-
/// 0b111000: Divide by 57
1068-
DIVIDE_57 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_57,
1069-
/// 0b111001: Divide by 58
1070-
DIVIDE_58 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_58,
1071-
/// 0b111010: Divide by 59
1072-
DIVIDE_59 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_59,
1073-
/// 0b111011: Divide by 60
1074-
DIVIDE_60 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_60,
1075-
/// 0b111100: Divide by 61
1076-
DIVIDE_61 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_61,
1077-
/// 0b111101: Divide by 62
1078-
DIVIDE_62 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_62,
1079-
/// 0b111110: Divide by 63
1080-
DIVIDE_63 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_63,
1081-
/// 0b111111: Divide by 64
1082-
DIVIDE_64 = ccm::CSCMR2::CAN_CLK_PODF::RW::DIVIDE_64,
928+
/// 0b1000: divide by 9
929+
#[cfg(features = "imxrt1011")]
930+
LPSPI_PODF_8 = ccm::CBCMR::LPSPI_PODF::RW::LPSPI_PODF_8,
931+
/// 0b1001: divide by 10
932+
#[cfg(features = "imxrt1011")]
933+
LPSPI_PODF_9 = ccm::CBCMR::LPSPI_PODF::RW::LPSPI_PODF_9,
934+
/// 0b1010: divide by 11
935+
#[cfg(features = "imxrt1011")]
936+
LPSPI_PODF_10 = ccm::CBCMR::LPSPI_PODF::RW::LPSPI_PODF_10,
937+
/// 0b1011: divide by 12
938+
#[cfg(features = "imxrt1011")]
939+
LPSPI_PODF_11 = ccm::CBCMR::LPSPI_PODF::RW::LPSPI_PODF_11,
940+
/// 0b1100: divide by 13
941+
#[cfg(features = "imxrt1011")]
942+
LPSPI_PODF_12 = ccm::CBCMR::LPSPI_PODF::RW::LPSPI_PODF_12,
943+
/// 0b1101: divide by 14
944+
#[cfg(features = "imxrt1011")]
945+
LPSPI_PODF_13 = ccm::CBCMR::LPSPI_PODF::RW::LPSPI_PODF_13,
946+
/// 0b1110: divide by 15
947+
#[cfg(features = "imxrt1011")]
948+
LPSPI_PODF_14 = ccm::CBCMR::LPSPI_PODF::RW::LPSPI_PODF_14,
949+
/// 0b1111: divide by 16
950+
#[cfg(features = "imxrt1011")]
951+
LPSPI_PODF_15 = ccm::CBCMR::LPSPI_PODF::RW::LPSPI_PODF_15,
1083952
}
1084953

1085954
impl From<ClockSelect> for Frequency {

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