feat: add axklib

Author: ZR233

Cargo.lock

@@ -17,10 +17,12 @@ members = [
     "modules/axsync",
     "modules/axtask",
     "modules/axipi",
+    "modules/axklib-impl",
 
     "api/axfeat",
     "api/arceos_api",
     "api/arceos_posix_api",
+    "api/axklib",
 
     "ulib/axstd",
     "ulib/axlibc",

Cargo.toml

@@ -0,0 +1,16 @@
+[package]
+name = "axklib"
+version.workspace = true
+edition.workspace = true
+authors = ["周睿 <zrufo747@outlook.com>"]
+license.workspace = true
+homepage.workspace = true
+documentation.workspace = true
+repository.workspace = true
+keywords.workspace = true
+categories.workspace = true
+
+[dependencies]
+trait-ffi = "0.2"
+memory_addr = "0.4"
+axerrno = "0.1"

api/axklib/Cargo.toml

@@ -0,0 +1,36 @@
+#![no_std]
+
+use core::time::Duration;
+
+pub use axerrno::AxResult;
+pub type IrqHandler = fn();
+pub use memory_addr::{PhysAddr, VirtAddr};
+
+use trait_ffi::*;
+
+#[def_extern_trait]
+pub trait Klib {
+    /// Maps a physical memory region to a virtual address space and returns the virtual address.
+    ///
+    /// The returned virtual address is guaranteed to be page-aligned.
+    fn mem_iomap(addr: PhysAddr, size: usize) -> AxResult<VirtAddr>;
+
+    fn time_busy_wait(dur: Duration);
+
+    fn irq_set_enable(irq: usize, enabled: bool);
+
+    fn irq_register(irq: usize, handler: IrqHandler) -> bool;
+}
+
+pub mod mem {
+    pub use super::klib::mem_iomap as iomap;
+}
+
+pub mod time {
+    pub use super::klib::time_busy_wait as busy_wait;
+}
+
+pub mod irq {
+    pub use super::klib::irq_register as register;
+    pub use super::klib::irq_set_enable as set_enable;
+}

api/axklib/src/lib.rs

@@ -0,0 +1,20 @@
+[package]
+authors = ["周睿 <zrufo747@outlook.com>"]
+categories.workspace = true
+documentation.workspace = true
+edition.workspace = true
+homepage.workspace = true
+keywords.workspace = true
+license.workspace = true
+name = "axklib-impl"
+repository.workspace = true
+version.workspace = true
+
+[features]
+irq = ["axhal/irq"]
+
+[dependencies]
+axhal = {workspace = true}
+axklib = {path = "../../api/axklib"}
+axmm = {workspace = true}
+trait-ffi = "0.2"

modules/axklib-impl/Cargo.toml

@@ -0,0 +1,37 @@
+#![no_std]
+
+use core::time::Duration;
+
+use axklib::*;
+
+struct KlibImpl;
+
+impl_trait! {
+    impl Klib for KlibImpl {
+        fn mem_iomap(addr: PhysAddr, size: usize) -> AxResult<VirtAddr> {
+            mem::iomap(addr, size)
+        }
+
+        fn time_busy_wait(dur: Duration) {
+            time::busy_wait(dur);
+        }
+
+        fn irq_set_enable(_irq: usize, _enabled: bool) {
+            #[cfg(feature = "irq")]
+            irq::set_enable(_irq, _enabled);
+            #[cfg(not(feature = "irq"))]
+            unimplemented!();
+        }
+
+        fn irq_register(_irq: usize, _handler: IrqHandler) -> bool {
+            #[cfg(feature = "irq")]
+            {
+                irq::register(_irq, _handler)
+            }
+            #[cfg(not(feature = "irq"))]
+            {
+                unimplemented!()
+            }
+        }
+    }
+}

modules/axklib-impl/src/lib.rs

@@ -112,3 +112,19 @@ pub fn init_memory_management() {
 pub fn init_memory_management_secondary() {
     unsafe { axhal::asm::write_kernel_page_table(kernel_page_table_root()) };
 }
+
+/// Maps a physical memory region to virtual address space for device access.
+pub fn iomap(addr: PhysAddr, size: usize) -> AxResult<VirtAddr> {
+    let virt = phys_to_virt(addr);
+
+    let virt_aligned = virt.align_down_4k();
+    let addr_aligned = addr.align_down_4k();
+    let size_aligned = (addr + size).align_up_4k() - addr_aligned;
+
+    let flags = MappingFlags::DEVICE | MappingFlags::READ | MappingFlags::WRITE;
+    let mut tb = kernel_aspace().lock();
+    tb.map_linear(virt_aligned, addr_aligned, size_aligned, flags)?;
+    // flush TLB
+    tb.protect(virt_aligned, size_aligned, flags)?;
+    Ok(virt)
+}