use 3 level ept paging

Author: Josen-B

Cargo.toml

@@ -15,6 +15,8 @@ repository = "https://github.com/arceos-hypervisor/arm_vcpu"
 categories = ["embedded", "no-std"]
 keywords = ["hypervisor", "aarch64", "vcpu"]
 
+[features]
+4-level-page = []
 
 [dependencies]
 log = "0.4"

src/vcpu.rs

@@ -171,27 +171,33 @@ impl<H: AxVCpuHal> Aarch64VCpu<H> {
         // - 4KiB granule (TG0)
         // - 39-bit address space (T0_SZ)
         // - start at level 1 (SL0)
-        // self.guest_system_regs.vtcr_el2 = (VTCR_EL2::PS::PA_40B_1TB
-        //     + VTCR_EL2::TG0::Granule4KB
-        //     + VTCR_EL2::SH0::Inner
-        //     + VTCR_EL2::ORGN0::NormalWBRAWA
-        //     + VTCR_EL2::IRGN0::NormalWBRAWA
-        //     + VTCR_EL2::SL0.val(0b01)
-        //     + VTCR_EL2::T0SZ.val(64 - 39))
-        // .into();
+        #[cfg(not(feature = "4-level-page"))]
+        {
+            self.guest_system_regs.vtcr_el2 = (VTCR_EL2::PS::PA_40B_1TB
+                + VTCR_EL2::TG0::Granule4KB
+                + VTCR_EL2::SH0::Inner
+                + VTCR_EL2::ORGN0::NormalWBRAWA
+                + VTCR_EL2::IRGN0::NormalWBRAWA
+                + VTCR_EL2::SL0.val(0b01)
+                + VTCR_EL2::T0SZ.val(64 - 39))
+            .into();
+        }
 
         // use 4 level ept paging
         // - 4KiB granule (TG0)
         // - 48-bit address space (T0_SZ)
         // - start at level 0 (SL0)
-        self.guest_system_regs.vtcr_el2 = (VTCR_EL2::PS::PA_48B_256TB
+        #[cfg(feature = "4-level-page")]
+        {
+            self.guest_system_regs.vtcr_el2 = (VTCR_EL2::PS::PA_48B_256TB
             + VTCR_EL2::TG0::Granule4KB
             + VTCR_EL2::SH0::Inner
             + VTCR_EL2::ORGN0::NormalWBRAWA
             + VTCR_EL2::IRGN0::NormalWBRAWA
             + VTCR_EL2::SL0.val(0b10) // 0b10 means start at level 0
             + VTCR_EL2::T0SZ.val(64 - 48))
-        .into();
+            .into();
+        }
 
         let mut hcr_el2 = HCR_EL2::VM::Enable
             + HCR_EL2::RW::EL1IsAarch64