Interrupt-injection and GPPT (#31)

* feat(vcpu): add interrupt injection support and enhance system register handling

- Add interrupt injection support to Aarch64VCpu
- Implement get_sysreg_device function for system register access
- Update GuestSystemRegisters to include CNTHCTL_EL2
- Modify exception handling to use SysRegAddr
- Adjust vcpu initialization to enable virtual IRQ and FIQ

* feat(sysreg): update handle_read and handle_write to use unused parameters

* update dependecies

* update percpu

* try setting ich_hcr_el2.en

* [feat] use 4 level paging for ept

* better code and comment for setting ich_hcr_el2

* add error messages for `current_el_sync_handler`

* pin rust toolchain version

* set `CNTHCTL_EL2::EL1PCEN` and `CNTHCTL_EL2::EL1PTCEN`, unset `HCR_EL2::IMO` to allow Guest to handle irqs themselves

* [STINKS] embed vgicv3 devices with HARD-CODED qemu gicv3 address location

* [feat] introduce set_return_value API

* [WIP!][TOBEREWRITE!] add gic-vdevice cofigs

* fixes after merging ivc code

* fix branch names for `axvcpu`

* emulate `ICC_SGI1R_EL1`

* update to newest dependencies

* de-coupling `arm_vcpu` and `arm_vgic`, fix some warnings

* fix a missing doc

* remove `arm_vgic` dependency

* add `builtin_sysreg_access_handler`, add interrupt and timer passthrough config

* remove sysreg emu devices

* rollback `tock-registers` to 0.9

* reformatted

---------

Co-authored-by: Debin <luodeb@outlook.com>
Co-authored-by: hky1999 <976929993@qq.com>

Author: 3 people

Cargo.toml

@@ -7,13 +7,14 @@ edition = "2024"
 log = "0.4.21"
 spin = "0.9"
 
-aarch64-cpu = "9.3"
-tock-registers = "0.8"
+aarch64-cpu = "10.0"
+tock-registers = "0.9"
 numeric-enum-macro = "0.2"
 
 axerrno = "0.1.0"
 percpu = { version = "0.2.0", features = ["arm-el2"] }
-aarch64_sysreg = "0.1.1"
 
 axaddrspace = { git = "https://github.com/arceos-hypervisor/axaddrspace.git" }
 axvcpu = { git = "https://github.com/arceos-hypervisor/axvcpu.git" }
+axdevice_base = { git = "https://github.com/arceos-hypervisor/axdevice_crates.git" }
+axvisor_api = { git = "https://github.com/arceos-hypervisor/axvisor_api.git" }

rust-toolchain.toml

@@ -0,0 +1,8 @@
+[toolchain]
+profile = "minimal"
+channel = "nightly-2024-12-25"
+components = ["rust-src", "llvm-tools", "rustfmt", "clippy"]
+targets = [
+    "aarch64-unknown-none",
+    "aarch64-unknown-none-softfloat",
+]

src/context_frame.rs

@@ -1,5 +1,4 @@
-use core::arch::asm;
-use core::fmt::Formatter;
+use core::{arch::asm, fmt::Formatter};
 
 use aarch64_cpu::registers::*;
 
@@ -156,6 +155,7 @@ pub struct GuestSystemRegisters {
     cntv_ctl_el0: u32,
     cntp_tval_el0: u32,
     cntv_tval_el0: u32,
+    pub cnthctl_el2: u64,
 
     // vpidr and vmpidr
     vpidr_el2: u32,
@@ -220,6 +220,7 @@ impl GuestSystemRegisters {
             asm!("mrs {0:x}, CNTP_TVAL_EL0", out(reg) self.cntp_tval_el0);
             asm!("mrs {0:x}, CNTV_TVAL_EL0", out(reg) self.cntv_tval_el0);
             asm!("mrs {0}, CNTVCT_EL0", out(reg) self.cntvct_el0);
+            asm!("mrs {0}, CNTHCTL_EL2", out(reg) self.cnthctl_el2);
             // MRS!("self.vpidr_el2, VPIDR_EL2, "x");
             asm!("mrs {0}, VMPIDR_EL2", out(reg) self.vmpidr_el2);
 
@@ -265,6 +266,7 @@ impl GuestSystemRegisters {
             asm!("msr CNTV_CVAL_EL0, {0}", in(reg) self.cntv_cval_el0);
             asm!("msr CNTKCTL_EL1, {0:x}", in (reg) self.cntkctl_el1);
             asm!("msr CNTV_CTL_EL0, {0:x}", in (reg) self.cntv_ctl_el0);
+            asm!("msr CNTHCTL_EL2, {0}", in(reg) self.cnthctl_el2);
             // The restoration of SP_EL0 is done in `exception_return_el2`,
             // which move the value from `self.ctx.sp_el0` to `SP_EL0`.
             // asm!("msr SP_EL0, {0}", in(reg) self.sp_el0);

src/exception.rs

@@ -1,10 +1,3 @@
-use aarch64_cpu::registers::{ESR_EL2, HCR_EL2, Readable, SCTLR_EL1, VTCR_EL2, VTTBR_EL2};
-
-use axaddrspace::GuestPhysAddr;
-use axaddrspace::device::AccessWidth;
-use axerrno::{AxError, AxResult};
-use axvcpu::AxVCpuExitReason;
-
 use crate::TrapFrame;
 use crate::exception_utils::{
     exception_class, exception_class_value, exception_data_abort_access_is_write,
@@ -15,6 +8,15 @@ use crate::exception_utils::{
     exception_sysreg_direction_write, exception_sysreg_gpr,
 };
 
+use aarch64_cpu::registers::{ESR_EL2, HCR_EL2, Readable, SCTLR_EL1, VTCR_EL2, VTTBR_EL2};
+use axaddrspace::{
+    GuestPhysAddr,
+    device::{AccessWidth, SysRegAddr},
+};
+use axerrno::{AxError, AxResult};
+use axvcpu::AxVCpuExitReason;
+use log::error;
+
 numeric_enum_macro::numeric_enum! {
 #[repr(u8)]
 #[derive(Debug)]
@@ -179,6 +181,7 @@ fn handle_data_abort(context_frame: &mut TrapFrame) -> AxResult<AxVCpuExitReason
         width,
         reg,
         reg_width,
+        signed_ext: false,
     })
 }
 
@@ -204,11 +207,14 @@ fn handle_system_register(context_frame: &mut TrapFrame) -> AxResult<AxVCpuExitR
     context_frame.set_exception_pc(val);
     if write {
         return Ok(AxVCpuExitReason::SysRegWrite {
-            addr,
+            addr: SysRegAddr::new(addr),
             value: context_frame.gpr(reg as usize) as u64,
         });
     }
-    Ok(AxVCpuExitReason::SysRegRead { addr, reg })
+    Ok(AxVCpuExitReason::SysRegRead {
+        addr: SysRegAddr::new(addr),
+        reg,
+    })
 }
 
 /// Handles HVC or SMC exceptions that serve as psci (Power State Coordination Interface) calls.
@@ -284,6 +290,14 @@ fn current_el_irq_handler(_tf: &mut TrapFrame) {
 /// Handles synchronous exceptions that occur from the current exception level.
 #[unsafe(no_mangle)]
 fn current_el_sync_handler(tf: &mut TrapFrame) {
+    let esr = ESR_EL2.extract();
+    let ec = ESR_EL2.read(ESR_EL2::EC);
+    let iss = ESR_EL2.read(ESR_EL2::ISS);
+
+    error!("ESR_EL2: {:#x}", esr.get());
+    error!("Exception Class: {:#x}", ec);
+    error!("Instruction Specific Syndrome: {:#x}", iss);
+
     panic!(
         "Unhandled synchronous exception from current EL: {:#x?}",
         tf

src/exception_utils.rs

@@ -1,8 +1,7 @@
 use aarch64_cpu::registers::{ESR_EL2, FAR_EL2, PAR_EL1};
-use tock_registers::interfaces::*;
-
 use axaddrspace::GuestPhysAddr;
 use axerrno::{AxResult, ax_err};
+use tock_registers::interfaces::*;
 
 /// Retrieves the Exception Syndrome Register (ESR) value from EL2.
 ///

src/lib.rs

@@ -15,7 +15,7 @@ mod smc;
 mod vcpu;
 
 pub use self::pcpu::Aarch64PerCpu;
-pub use self::vcpu::{Aarch64VCpu, Aarch64VCpuCreateConfig};
+pub use self::vcpu::{Aarch64VCpu, Aarch64VCpuCreateConfig, Aarch64VCpuSetupConfig};
 
 /// context frame for aarch64
 pub type TrapFrame = context_frame::Aarch64ContextFrame;

src/pcpu.rs

@@ -1,10 +1,9 @@
 use core::{cell::OnceCell, marker::PhantomData};
 
 use aarch64_cpu::registers::*;
-use tock_registers::interfaces::ReadWriteable;
-
 use axerrno::AxResult;
 use axvcpu::{AxArchPerCpu, AxVCpuHal};
+use tock_registers::interfaces::ReadWriteable;
 
 /// Per-CPU data. A pointer to this struct is loaded into TP when a CPU starts. This structure
 #[repr(C)]
@@ -64,6 +63,19 @@ impl<H: AxVCpuHal> AxArchPerCpu for Aarch64PerCpu<H> {
                 + HCR_EL2::TSC::EnableTrapEl1SmcToEl2,
         );
 
+        // Note that `ICH_HCR_EL2` is not the same as `HCR_EL2`.
+        //
+        // `ICH_HCR_EL2[0]` controls the virtual CPU interface operation.
+        //
+        // We leave it for the virtual GIC implementations to decide whether to enable it or not.
+        //
+        // unsafe {
+        //     core::arch::asm! {
+        //         "msr ich_hcr_el2, {value:x}",
+        //         value = in(reg) 0,
+        //     }
+        // }
+
         Ok(())
     }