feat(vcpu): add support for emulated system registers and update exception handling

- Add axdevice and axhal dependencies in Cargo.toml
- Implement CNTHCTL_EL2 register in GuestSystemRegisters
- Update exception handling to use LOWER_SYNC_VCPU
- Add Aarch64EmuRegs and update vcpu.rs for emulated registers
- Modify HCR_EL2 configuration in vcpu initialization

Author: luodeb

Cargo.toml

@@ -17,3 +17,5 @@ aarch64_sysreg = "0.1.1"
 
 axaddrspace = { git = "https://github.com/arceos-hypervisor/axaddrspace.git" }
 axvcpu = { git = "https://github.com/arceos-hypervisor/axvcpu.git" }
+axdevice = { git = "https://github.com/arceos-hypervisor/axdevice.git" }
+axhal = { git = "https://github.com/arceos-hypervisor/arceos.git", branch = "vmm_rebase" }

src/context_frame.rs

@@ -156,6 +156,7 @@ pub struct GuestSystemRegisters {
     cntv_ctl_el0: u32,
     cntp_tval_el0: u32,
     cntv_tval_el0: u32,
+    pub cnthctl_el2: u64,
 
     // vpidr and vmpidr
     vpidr_el2: u32,
@@ -220,6 +221,7 @@ impl GuestSystemRegisters {
             asm!("mrs {0:x}, CNTP_TVAL_EL0", out(reg) self.cntp_tval_el0);
             asm!("mrs {0:x}, CNTV_TVAL_EL0", out(reg) self.cntv_tval_el0);
             asm!("mrs {0}, CNTVCT_EL0", out(reg) self.cntvct_el0);
+            asm!("mrs {0}, CNTHCTL_EL2", out(reg) self.cnthctl_el2);
             // MRS!("self.vpidr_el2, VPIDR_EL2, "x");
             asm!("mrs {0}, VMPIDR_EL2", out(reg) self.vmpidr_el2);
 
@@ -265,6 +267,7 @@ impl GuestSystemRegisters {
             asm!("msr CNTV_CVAL_EL0, {0}", in(reg) self.cntv_cval_el0);
             asm!("msr CNTKCTL_EL1, {0:x}", in (reg) self.cntkctl_el1);
             asm!("msr CNTV_CTL_EL0, {0:x}", in (reg) self.cntv_ctl_el0);
+            asm!("msr CNTHCTL_EL2, {0}", in(reg) self.cnthctl_el2);
             // The restoration of SP_EL0 is done in `exception_return_el2`,
             // which move the value from `self.ctx.sp_el0` to `SP_EL0`.
             // asm!("msr SP_EL0, {0}", in(reg) self.sp_el0);

src/exception.S

@@ -110,7 +110,7 @@ exception_vector_base_vcpu:
     INVALID_EXCP_EL2 3 0
 
     // current EL, with SP_ELx
-    HANDLE_CURRENT_SYNC
+    HANDLE_LOWER_SYNC_VCPU
     HANDLE_CURRENT_IRQ
     INVALID_EXCP_EL2 2 1
     INVALID_EXCP_EL2 3 1

src/lib.rs

@@ -12,9 +12,11 @@ mod exception_utils;
 mod exception;
 mod pcpu;
 mod smc;
+mod system_registers;
 mod vcpu;
 
 pub use self::pcpu::Aarch64PerCpu;
+pub use self::system_registers::Aarch64EmuRegs;
 pub use self::vcpu::{Aarch64VCpu, Aarch64VCpuCreateConfig};
 
 /// context frame for aarch64

src/system_registers.rs

@@ -0,0 +1,154 @@
+extern crate alloc;
+use crate::vcpu::Aarch64VCpu;
+use aarch64_cpu::registers::{Readable, Writeable};
+use aarch64_cpu::registers::{CNTFRQ_EL0, CNTPCT_EL0, CNTP_CTL_EL0, CNTP_TVAL_EL0};
+use aarch64_sysreg::SystemRegType;
+use alloc::sync::Arc;
+use alloc::vec::Vec;
+use axdevice::timer::{register_timer, VmmTimerEvent};
+use axvcpu::{AxVCpu, AxVCpuHal};
+use spin::RwLock;
+
+use axhal::irq::MyVgic;
+
+type RegVcpu<H> = Arc<AxVCpu<Aarch64VCpu<H>>>;
+
+use core::arch::asm;
+fn get_mpidr() -> u64 {
+    let mpidr: u64;
+    unsafe {
+        asm!(
+          "mrs {mpidr}, MPIDR_EL1", // 从 MPIDR_EL1 读取
+          mpidr = out(reg) mpidr
+        );
+    }
+    mpidr
+}
+
+/// Struct representing an entry in the emulator register list.
+pub struct EmuRegEntry<H: AxVCpuHal> {
+    /// The type of the emulator register.
+    pub emu_type: EmuRegType,
+    /// The address associated with the emulator register.
+    pub addr: SystemRegType,
+    /// The handler write function for the emulator register.
+    pub handle_write: fn(SystemRegType, u64, RegVcpu<H>) -> bool,
+    /// The handler read function for the emulator register.
+    pub handle_read: fn(SystemRegType, usize, RegVcpu<H>) -> bool,
+}
+
+/// Enumeration representing the type of emulator registers.
+pub enum EmuRegType {
+    /// System register type for emulator registers.
+    SysReg,
+}
+
+/// Struct representing the emulator registers.
+pub struct Aarch64EmuRegs<H: AxVCpuHal> {
+    /// The list of emulator registers.
+    pub emu_regs: RwLock<Vec<EmuRegEntry<H>>>,
+}
+
+impl<H: AxVCpuHal> Aarch64EmuRegs<H> {
+    const EMU_REGISTERS: [EmuRegEntry<H>; 3] = [
+        EmuRegEntry {
+            emu_type: EmuRegType::SysReg,
+            addr: SystemRegType::CNTP_TVAL_EL0,
+            handle_write: |addr, value, vcpu| {
+                debug!(
+                    "Write to emulator register: {:?}, value: {}, vcpu: {}, {}",
+                    addr,
+                    value,
+                    vcpu.id(),
+                    get_mpidr()
+                );
+                // CNTP_TVAL_EL0.set(value);
+                let now = axhal::time::monotonic_time_nanos();
+                trace!("Current time: {}", now);
+                let gich = MyVgic::get_gich();
+                register_timer(
+                    value + now,
+                    VmmTimerEvent::new(|_| {
+                        debug!("Timer expired");
+                        let gich = MyVgic::get_gich();
+                        let hcr = gich.get_hcr();
+                        gich.set_hcr(hcr | 1 << 0);
+                        let mut lr = 0;
+                        lr |= 30 << 0;
+                        lr |= 1 << 19;
+                        lr |= 1 << 28;
+                        gich.set_lr(0, lr);
+                    }),
+                );
+                true
+            },
+            handle_read: |_, _, _| true,
+        },
+        EmuRegEntry {
+            emu_type: EmuRegType::SysReg,
+            addr: SystemRegType::CNTP_CTL_EL0,
+            handle_write: |addr, value, _| {
+                trace!("Write to emulator register: {:?}, value: {}", addr, value);
+                // if value & 0x1 != 0 {
+                //     axhal::irq::set_enable(30, true);
+                // } else {
+                //     axhal::irq::set_enable(30, false);
+                // }
+
+                // let gich = MyVgic::get_gich();
+                // let gicd = MyVgic::get_gicd();
+                // let gicc = MyVgic::get_gicv();
+                // CNTP_CTL_EL0.set(value);
+                // let hcr = gich.get_hcr();
+                // gich.set_hcr(hcr | 1 << 0);
+                // let mut lr = 0;
+                // lr |= 30 << 0;
+                // lr |= 1 << 19;
+                // lr |= 1 << 28;
+                // gich.set_lr(0, lr);
+                // gicd.lock().set_pend(30, true, 0);
+                // gicc.set_ctlr(ctlr);
+
+                true
+            },
+            handle_read: |_, _, _| true,
+        },
+        EmuRegEntry {
+            emu_type: EmuRegType::SysReg,
+            addr: SystemRegType::CNTPCT_EL0,
+            handle_write: |_, _, _| true,
+            handle_read: |addr, reg, vcpu| {
+                let val = CNTPCT_EL0.get();
+                trace!("Read from emulator register: {:?}, value: {}", addr, val);
+                vcpu.set_gpr(reg, val as usize);
+                true
+            },
+        },
+    ];
+
+    /// Handle a write to an emulator register.
+    pub fn emu_register_handle_write(addr: SystemRegType, value: u64, vcpu: RegVcpu<H>) -> bool {
+        let emu_reg = Self::EMU_REGISTERS;
+
+        for entry in emu_reg.iter() {
+            if entry.addr == addr {
+                return (entry.handle_write)(addr, value, vcpu);
+            }
+        }
+        error!("Invalid emulated register write: {}", addr);
+        false
+    }
+
+    /// Handle a read from an emulator register.
+    pub fn emu_register_handle_read(addr: SystemRegType, reg: usize, vcpu: RegVcpu<H>) -> bool {
+        let emu_reg = Self::EMU_REGISTERS;
+
+        for entry in emu_reg.iter() {
+            if entry.addr == addr {
+                return (entry.handle_read)(addr, reg, vcpu);
+            }
+        }
+        error!("Invalid emulated register read: {}", addr);
+        false
+    }
+}

src/vcpu.rs

@@ -1,16 +1,16 @@
 use core::marker::PhantomData;
 
-use aarch64_cpu::registers::{CNTHCTL_EL2, HCR_EL2, SP_EL0, SPSR_EL1, VTCR_EL2};
+use aarch64_cpu::registers::{CNTHCTL_EL2, HCR_EL2, SPSR_EL1, SP_EL0, VTCR_EL2};
 use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
 
 use axaddrspace::{GuestPhysAddr, HostPhysAddr};
 use axerrno::AxResult;
 use axvcpu::{AxVCpuExitReason, AxVCpuHal};
 
-use crate::TrapFrame;
 use crate::context_frame::GuestSystemRegisters;
-use crate::exception::{TrapKind, handle_exception_sync};
+use crate::exception::{handle_exception_sync, TrapKind};
 use crate::exception_utils::exception_class_value;
+use crate::TrapFrame;
 
 #[percpu::def_percpu]
 static HOST_SP_EL0: u64 = 0;
@@ -151,9 +151,13 @@ impl<H: AxVCpuHal> Aarch64VCpu<H> {
             + VTCR_EL2::SL0.val(0b01)
             + VTCR_EL2::T0SZ.val(64 - 39))
         .into();
-        self.guest_system_regs.hcr_el2 =
-            (HCR_EL2::VM::Enable + HCR_EL2::RW::EL1IsAarch64 + HCR_EL2::TSC::EnableTrapEl1SmcToEl2)
-                .into();
+        self.guest_system_regs.hcr_el2 = (HCR_EL2::VM::Enable
+            + HCR_EL2::RW::EL1IsAarch64
+            + HCR_EL2::IMO::EnableVirtualIRQ
+            + HCR_EL2::FMO::EnableVirtualFIQ
+            + HCR_EL2::TSC::EnableTrapEl1SmcToEl2
+            + HCR_EL2::RW::EL1IsAarch64)
+            .into();
         // self.system_regs.hcr_el2 |= 1<<27;
         // + HCR_EL2::IMO::EnableVirtualIRQ).into();
 
@@ -203,7 +207,13 @@ impl<H: AxVCpuHal> Aarch64VCpu<H> {
         }
 
         // the dummy return value, the real return value is in x0 when `return_run_guest` returns
-        0
+        let exit_reason: usize;
+        core::arch::asm!(
+            "mov {}, x0",
+            out(reg) exit_reason,
+            options(nostack)
+        );
+        exit_reason
     }
 
     /// Restores guest system control registers.