emulate ICC_SGI1R_EL1

Author: aarkegz

src/gic/mod.rs

@@ -3,7 +3,10 @@ extern crate alloc;
 use core::result;
 
 use alloc::{sync::Arc, vec, vec::Vec};
-use arm_vgic::{v3::{gits::Gits, vgicd::VGicD, vgicr::VGicR}, vgic};
+use arm_vgic::{
+    v3::{gits::Gits, vgicd::VGicD, vgicr::VGicR},
+    vgic,
+};
 use axaddrspace::{GuestPhysAddr, HostPhysAddr};
 use axdevice_base::BaseMmioDeviceOps;
 
@@ -44,7 +47,11 @@ pub fn get_gic_devices(config: GicDeviceConfig) -> Vec<Arc<dyn BaseMmioDeviceOps
     let mut gicd = VGicD::new(config.gicd_base, None);
 
     for assigned_spi in config.assigned_spis {
-        gicd.assign_irq(assigned_spi.spi, assigned_spi.target_cpu_phys_id, assigned_spi.target_cpu_affinity);
+        gicd.assign_irq(
+            assigned_spi.spi,
+            assigned_spi.target_cpu_phys_id,
+            assigned_spi.target_cpu_affinity,
+        );
     }
 
     results.push(Arc::new(gicd));
@@ -62,13 +69,11 @@ pub fn get_gic_devices(config: GicDeviceConfig) -> Vec<Arc<dyn BaseMmioDeviceOps
 
     results
 
-
     // let mut vgicd = VGicD::new(0x0800_0000.into(), None);
 
     // vgicd.assigned_irqs.set(0x28, true);
     // // vgicd.assigned_irqs.set(0x1, true);
 
-
     // let vgicr0 = VGicR::new(0x080a_0000.into(), None, 0);
     // let vgicr1 = VGicR::new(0x080c_0000.into(), None, 1);
     // let vgicr2 = VGicR::new(0x080e_0000.into(), None, 2);

src/vcpu.rs

@@ -1,6 +1,7 @@
 use core::marker::PhantomData;
 
 use aarch64_cpu::registers::{CNTHCTL_EL2, HCR_EL2, SP_EL0, SPSR_EL1, VTCR_EL2};
+use axaddrspace::device::SysRegAddr;
 use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
 
 use crate::TrapFrame;
@@ -303,14 +304,46 @@ impl<H: AxVCpuHal> Aarch64VCpu<H> {
             _ => panic!("Unhandled exception {:?}", exit_reason),
         };
 
+        const SYSREG_ICC_SGI1R_EL1: SysRegAddr = SysRegAddr::new(0x3A_3016); // ICC_SGI1R_EL1
         match result {
-            Ok(AxVCpuExitReason::MmioRead {
-                addr,
-                width,
-                reg,
-                reg_width,
-            }) if false => {}
-            Ok(AxVCpuExitReason::MmioWrite { addr, width, data }) if false => {}
+            Ok(AxVCpuExitReason::SysRegWrite { addr, value }) if addr == SYSREG_ICC_SGI1R_EL1 => {
+                debug!("arm_vcpu ICC_SGI1R_EL1 write: {:#x}", value);
+
+                // TODO: support RangeSelector
+
+                let intid = (value >> 24) & 0b1111;
+                let irm = ((value >> 40) & 0b1) != 0;
+
+                // IRM == 1 => send to all except self
+                if irm {
+                    debug!("arm_vcpu ICC_SGI1R_EL1 write: irm == 1, send to all except self");
+
+                    return Ok(AxVCpuExitReason::SendIPI {
+                        target_cpu: 0,
+                        target_cpu_aux: 0,
+                        send_to_all: true,
+                        send_to_self: false,
+                        vector: intid,
+                    });
+                }
+
+                let aff3 = (value >> 48) & 0xff;
+                let aff2 = (value >> 32) & 0xff;
+                let aff1 = (value >> 16) & 0xff;
+                let target_list = (value & 0xffff);
+
+                debug!(
+                    "arm_vcpu ICC_SGI1R_EL1 write: aff3:{:#x} aff2:{:#x} aff1:{:#x} intid:{:#x} target_list:{:#x}",
+                    aff3, aff2, aff1, intid, target_list
+                );
+                return Ok(AxVCpuExitReason::SendIPI {
+                    target_cpu: (aff3 << 24) | (aff2 << 16) | (aff1 << 8),
+                    target_cpu_aux: target_list,
+                    send_to_all: false,
+                    send_to_self: false,
+                    vector: intid,
+                });
+            }
             r => return r,
         }