feat(vcpu): add interrupt injection support and enhance system register handling

- Add interrupt injection support to Aarch64VCpu
- Implement get_sysreg_device function for system register access
- Update GuestSystemRegisters to include CNTHCTL_EL2
- Modify exception handling to use SysRegAddr
- Adjust vcpu initialization to enable virtual IRQ and FIQ

Author: luodeb

Cargo.toml

@@ -17,3 +17,6 @@ aarch64_sysreg = "0.1.1"
 
 axaddrspace = { git = "https://github.com/arceos-hypervisor/axaddrspace.git" }
 axvcpu = { git = "https://github.com/arceos-hypervisor/axvcpu.git" }
+axhal = { git = "https://github.com/arceos-hypervisor/arceos.git", branch = "vmm_inject_interrupt" }
+axdevice_base = { git = "https://github.com/arceos-hypervisor/axdevice_crates.git"}
+axvisor_api = { git = "https://github.com/arceos-hypervisor/axvisor_api.git", branch = "inject_interrupt" }

src/context_frame.rs

@@ -156,6 +156,7 @@ pub struct GuestSystemRegisters {
     cntv_ctl_el0: u32,
     cntp_tval_el0: u32,
     cntv_tval_el0: u32,
+    pub cnthctl_el2: u64,
 
     // vpidr and vmpidr
     vpidr_el2: u32,
@@ -220,6 +221,7 @@ impl GuestSystemRegisters {
             asm!("mrs {0:x}, CNTP_TVAL_EL0", out(reg) self.cntp_tval_el0);
             asm!("mrs {0:x}, CNTV_TVAL_EL0", out(reg) self.cntv_tval_el0);
             asm!("mrs {0}, CNTVCT_EL0", out(reg) self.cntvct_el0);
+            asm!("mrs {0}, CNTHCTL_EL2", out(reg) self.cnthctl_el2);
             // MRS!("self.vpidr_el2, VPIDR_EL2, "x");
             asm!("mrs {0}, VMPIDR_EL2", out(reg) self.vmpidr_el2);
 
@@ -265,6 +267,7 @@ impl GuestSystemRegisters {
             asm!("msr CNTV_CVAL_EL0, {0}", in(reg) self.cntv_cval_el0);
             asm!("msr CNTKCTL_EL1, {0:x}", in (reg) self.cntkctl_el1);
             asm!("msr CNTV_CTL_EL0, {0:x}", in (reg) self.cntv_ctl_el0);
+            asm!("msr CNTHCTL_EL2, {0}", in(reg) self.cnthctl_el2);
             // The restoration of SP_EL0 is done in `exception_return_el2`,
             // which move the value from `self.ctx.sp_el0` to `SP_EL0`.
             // asm!("msr SP_EL0, {0}", in(reg) self.sp_el0);

src/exception.rs

@@ -1,9 +1,5 @@
 use aarch64_cpu::registers::{ESR_EL2, HCR_EL2, Readable, SCTLR_EL1, VTCR_EL2, VTTBR_EL2};
 
-use axaddrspace::GuestPhysAddr;
-use axerrno::{AxError, AxResult};
-use axvcpu::{AccessWidth, AxVCpuExitReason};
-
 use crate::TrapFrame;
 use crate::exception_utils::{
     exception_class, exception_class_value, exception_data_abort_access_is_write,
@@ -13,6 +9,10 @@ use crate::exception_utils::{
     exception_esr, exception_fault_addr, exception_next_instruction_step, exception_sysreg_addr,
     exception_sysreg_direction_write, exception_sysreg_gpr,
 };
+use axaddrspace::GuestPhysAddr;
+use axaddrspace::device::{AccessWidth, SysRegAddr};
+use axerrno::{AxError, AxResult};
+use axvcpu::AxVCpuExitReason;
 
 numeric_enum_macro::numeric_enum! {
 #[repr(u8)]
@@ -203,11 +203,14 @@ fn handle_system_register(context_frame: &mut TrapFrame) -> AxResult<AxVCpuExitR
     context_frame.set_exception_pc(val);
     if write {
         return Ok(AxVCpuExitReason::SysRegWrite {
-            addr,
+            addr: SysRegAddr::new(addr),
             value: context_frame.gpr(reg as usize) as u64,
         });
     }
-    Ok(AxVCpuExitReason::SysRegRead { addr, reg })
+    Ok(AxVCpuExitReason::SysRegRead {
+        addr: SysRegAddr::new(addr),
+        reg,
+    })
 }
 
 /// Handles HVC or SMC exceptions that serve as psci (Power State Coordination Interface) calls.

src/lib.rs

@@ -13,7 +13,9 @@ mod exception;
 mod pcpu;
 mod smc;
 mod vcpu;
+mod sysreg;
 
+pub use self::sysreg::get_sysreg_device;
 pub use self::pcpu::Aarch64PerCpu;
 pub use self::vcpu::{Aarch64VCpu, Aarch64VCpuCreateConfig};
 

src/sysreg/cntp_ctl_el0.rs

@@ -0,0 +1,50 @@
+use aarch64_sysreg::SystemRegType;
+
+use axaddrspace::GuestPhysAddrRange;
+use axaddrspace::device::{AccessWidth, DeviceAddrRange, SysRegAddr, SysRegAddrRange};
+use axdevice_base::EmuDeviceType;
+use axdevice_base::{BaseDeviceOps, BaseMmioDeviceOps};
+use axerrno::AxResult;
+
+impl BaseDeviceOps<SysRegAddrRange> for SysCntpCtlEl0 {
+    fn emu_type(&self) -> EmuDeviceType {
+        EmuDeviceType::EmuDeviceTConsole
+    }
+
+    fn address_range(&self) -> SysRegAddrRange {
+        SysRegAddrRange {
+            start: SysRegAddr::new(SystemRegType::CNTP_CTL_EL0 as usize),
+            end: SysRegAddr::new(SystemRegType::CNTP_CTL_EL0 as usize),
+        }
+    }
+
+    fn handle_read(
+        &self,
+        addr: <SysRegAddrRange as DeviceAddrRange>::Addr,
+        width: AccessWidth,
+    ) -> AxResult<usize> {
+        todo!()
+    }
+
+    fn handle_write(
+        &self,
+        addr: <SysRegAddrRange as DeviceAddrRange>::Addr,
+        width: AccessWidth,
+        val: usize,
+    ) -> AxResult {
+        info!("Write to emulator register: {:?}, value: {}", addr, val);
+        Ok(())
+    }
+}
+
+pub struct SysCntpCtlEl0 {
+    // Fields
+}
+
+impl SysCntpCtlEl0 {
+    pub fn new() -> Self {
+        Self {
+            // Initialize fields
+        }
+    }
+}

src/sysreg/cntp_tval_el0.rs

@@ -0,0 +1,72 @@
+extern crate alloc;
+
+use aarch64_sysreg::SystemRegType;
+
+use aarch64_cpu::registers::{CNTPCT_EL0, Readable};
+
+use axaddrspace::{
+    GuestPhysAddrRange,
+    device::{AccessWidth, DeviceAddrRange, SysRegAddr, SysRegAddrRange},
+};
+
+use axdevice_base::{BaseDeviceOps, EmuDeviceType};
+
+use axhal::irq::inject_interrupt;
+use axvisor_api::time::{current_time_nanos, register_timer};
+
+use core::time::Duration;
+
+use alloc::boxed::Box;
+
+use axerrno::AxResult;
+
+impl BaseDeviceOps<SysRegAddrRange> for SysCntpTvalEl0 {
+    fn emu_type(&self) -> EmuDeviceType {
+        EmuDeviceType::EmuDeviceTConsole
+    }
+
+    fn address_range(&self) -> SysRegAddrRange {
+        SysRegAddrRange {
+            start: SysRegAddr::new(SystemRegType::CNTP_TVAL_EL0 as usize),
+            end: SysRegAddr::new(SystemRegType::CNTP_TVAL_EL0 as usize),
+        }
+    }
+
+    fn handle_read(
+        &self,
+        addr: <SysRegAddrRange as DeviceAddrRange>::Addr,
+        width: AccessWidth,
+    ) -> AxResult<usize> {
+        todo!()
+    }
+
+    fn handle_write(
+        &self,
+        addr: <SysRegAddrRange as DeviceAddrRange>::Addr,
+        width: AccessWidth,
+        val: usize,
+    ) -> AxResult {
+        info!("Write to emulator register: {:?}, value: {}", addr, val);
+        let now = current_time_nanos();
+        info!("Current time: {}, deadline: {}", now, now + val as u64);
+        register_timer(
+            Duration::from_nanos(now + val as u64),
+            Box::new(|_| {
+                inject_interrupt(30);
+            }),
+        );
+        Ok(())
+    }
+}
+
+pub struct SysCntpTvalEl0 {
+    // Fields
+}
+
+impl SysCntpTvalEl0 {
+    pub fn new() -> Self {
+        Self {
+            // Initialize fields
+        }
+    }
+}

src/sysreg/cntpct_el0.rs

@@ -0,0 +1,55 @@
+use aarch64_sysreg::SystemRegType;
+
+use aarch64_cpu::registers::{CNTPCT_EL0, Readable};
+
+use axaddrspace::{
+    GuestPhysAddrRange,
+    device::{AccessWidth, DeviceAddrRange, SysRegAddr, SysRegAddrRange},
+};
+
+use axdevice_base::{BaseDeviceOps, EmuDeviceType};
+
+use axerrno::AxResult;
+
+impl BaseDeviceOps<SysRegAddrRange> for SysCntpctEl0 {
+    fn emu_type(&self) -> EmuDeviceType {
+        EmuDeviceType::EmuDeviceTConsole
+    }
+
+    fn address_range(&self) -> SysRegAddrRange {
+        SysRegAddrRange {
+            start: SysRegAddr::new(SystemRegType::CNTPCT_EL0 as usize),
+            end: SysRegAddr::new(SystemRegType::CNTPCT_EL0 as usize),
+        }
+    }
+
+    fn handle_read(
+        &self,
+        addr: <SysRegAddrRange as DeviceAddrRange>::Addr,
+        width: AccessWidth,
+    ) -> AxResult<usize> {
+        Ok(CNTPCT_EL0.get() as usize)
+    }
+
+    fn handle_write(
+        &self,
+        addr: <SysRegAddrRange as DeviceAddrRange>::Addr,
+        width: AccessWidth,
+        val: usize,
+    ) -> AxResult {
+        info!("Write to emulator register: {:?}, value: {}", addr, val);
+        Ok(())
+    }
+}
+
+pub struct SysCntpctEl0 {
+    // Fields
+}
+
+impl SysCntpctEl0 {
+    pub fn new() -> Self {
+        Self {
+            // Initialize fields
+        }
+    }
+}

src/sysreg/mod.rs

@@ -0,0 +1,22 @@
+extern crate alloc;
+
+use alloc::sync::Arc;
+use alloc::{vec, vec::Vec};
+use axdevice_base::BaseSysRegDeviceOps;
+
+mod cntp_ctl_el0;
+pub use cntp_ctl_el0::SysCntpCtlEl0;
+
+mod cntpct_el0;
+pub use cntpct_el0::SysCntpctEl0;
+
+mod cntp_tval_el0;
+pub use cntp_tval_el0::SysCntpTvalEl0;
+
+pub fn get_sysreg_device() -> Vec<Arc<dyn BaseSysRegDeviceOps>> {
+    vec![
+        Arc::new(SysCntpCtlEl0::new()),
+        Arc::new(SysCntpctEl0::new()),
+        Arc::new(SysCntpTvalEl0::new()),
+    ]
+}

src/vcpu.rs

@@ -3,14 +3,14 @@ use core::marker::PhantomData;
 use aarch64_cpu::registers::{CNTHCTL_EL2, HCR_EL2, SP_EL0, SPSR_EL1, VTCR_EL2};
 use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
 
-use axaddrspace::{GuestPhysAddr, HostPhysAddr};
-use axerrno::AxResult;
-use axvcpu::{AxVCpuExitReason, AxVCpuHal};
-
 use crate::TrapFrame;
 use crate::context_frame::GuestSystemRegisters;
 use crate::exception::{TrapKind, handle_exception_sync};
 use crate::exception_utils::exception_class_value;
+use axaddrspace::{GuestPhysAddr, HostPhysAddr};
+use axerrno::AxResult;
+use axhal::irq::inject_interrupt;
+use axvcpu::{AxVCpuExitReason, AxVCpuHal};
 
 #[percpu::def_percpu]
 static HOST_SP_EL0: u64 = 0;
@@ -121,6 +121,11 @@ impl<H: AxVCpuHal> axvcpu::AxArchVCpu for Aarch64VCpu<H> {
     fn set_gpr(&mut self, idx: usize, val: usize) {
         self.ctx.set_gpr(idx, val);
     }
+
+    fn inject_interrupt(&mut self, vector: usize) -> AxResult {
+        inject_interrupt(vector);
+        Ok(())
+    }
 }
 
 // Private function
@@ -151,9 +156,13 @@ impl<H: AxVCpuHal> Aarch64VCpu<H> {
             + VTCR_EL2::SL0.val(0b01)
             + VTCR_EL2::T0SZ.val(64 - 39))
         .into();
-        self.guest_system_regs.hcr_el2 =
-            (HCR_EL2::VM::Enable + HCR_EL2::RW::EL1IsAarch64 + HCR_EL2::TSC::EnableTrapEl1SmcToEl2)
-                .into();
+        self.guest_system_regs.hcr_el2 = (HCR_EL2::VM::Enable
+            + HCR_EL2::RW::EL1IsAarch64
+            + HCR_EL2::IMO::EnableVirtualIRQ
+            + HCR_EL2::FMO::EnableVirtualFIQ
+            + HCR_EL2::TSC::EnableTrapEl1SmcToEl2
+            + HCR_EL2::RW::EL1IsAarch64)
+            .into();
         // self.system_regs.hcr_el2 |= 1<<27;
         // + HCR_EL2::IMO::EnableVirtualIRQ).into();
 
@@ -203,7 +212,14 @@ impl<H: AxVCpuHal> Aarch64VCpu<H> {
         }
 
         // the dummy return value, the real return value is in x0 when `return_run_guest` returns
-        0
+        let exit_reason: usize;
+        core::arch::asm!(
+            "mov {}, x0",
+            out(reg) exit_reason,
+            options(nostack)
+        );
+        exit_reason
+        
     }
 
     /// Restores guest system control registers.