|
| 1 | +/dts-v1/; |
| 2 | + |
| 3 | +/memreserve/ 0x0000000080000000 0x0000000000010000; |
| 4 | +/ { |
| 5 | + compatible = "phytium,pe2204"; |
| 6 | + interrupt-parent = <0x01>; |
| 7 | + #address-cells = <0x02>; |
| 8 | + #size-cells = <0x02>; |
| 9 | + model = "Phytium Pi Board"; |
| 10 | + |
| 11 | + // memory@01 { |
| 12 | + // device_type = "memory"; |
| 13 | + // reg = <0x20 0x00 0x00 0x80000000>; |
| 14 | + // numa-node-id = <0x00>; |
| 15 | + // }; |
| 16 | + |
| 17 | + aliases { |
| 18 | + serial1 = "/soc/uart@2800d000"; |
| 19 | + }; |
| 20 | + |
| 21 | + psci { |
| 22 | + compatible = "arm,psci-1.0"; |
| 23 | + method = "smc"; |
| 24 | + cpu_suspend = <0xc4000001>; |
| 25 | + cpu_off = <0x84000002>; |
| 26 | + cpu_on = <0xc4000003>; |
| 27 | + sys_poweroff = <0x84000008>; |
| 28 | + sys_reset = <0x84000009>; |
| 29 | + }; |
| 30 | + |
| 31 | + cpus { |
| 32 | + #address-cells = <0x02>; |
| 33 | + #size-cells = <0x00>; |
| 34 | + |
| 35 | + cpu-map { |
| 36 | + |
| 37 | + // cluster0 { |
| 38 | + |
| 39 | + // core0 { |
| 40 | + // cpu = <0x05>; |
| 41 | + // }; |
| 42 | + // }; |
| 43 | + |
| 44 | + // cluster1 { |
| 45 | + |
| 46 | + // core0 { |
| 47 | + // cpu = <0x06>; |
| 48 | + // }; |
| 49 | + // }; |
| 50 | + |
| 51 | + cluster2 { |
| 52 | + |
| 53 | + core0 { |
| 54 | + cpu = <0x07>; |
| 55 | + }; |
| 56 | + |
| 57 | + // core1 { |
| 58 | + // cpu = <0x08>; |
| 59 | + // }; |
| 60 | + }; |
| 61 | + }; |
| 62 | + |
| 63 | + cpu@0 { |
| 64 | + device_type = "cpu"; |
| 65 | + compatible = "phytium,ftc310\0arm,armv8"; |
| 66 | + reg = <0x00 0x200>; |
| 67 | + enable-method = "psci"; |
| 68 | + clocks = <0x09 0x02>; |
| 69 | + capacity-dmips-mhz = <0xb22>; |
| 70 | + phandle = <0x07>; |
| 71 | + }; |
| 72 | + |
| 73 | + // cpu@1 { |
| 74 | + // device_type = "cpu"; |
| 75 | + // compatible = "phytium,ftc310\0arm,armv8"; |
| 76 | + // reg = <0x00 0x201>; |
| 77 | + // enable-method = "psci"; |
| 78 | + // clocks = <0x09 0x02>; |
| 79 | + // capacity-dmips-mhz = <0xb22>; |
| 80 | + // phandle = <0x08>; |
| 81 | + // }; |
| 82 | + |
| 83 | + // cpu@100 { |
| 84 | + // device_type = "cpu"; |
| 85 | + // compatible = "phytium,ftc664\0arm,armv8"; |
| 86 | + // reg = <0x00 0x00>; |
| 87 | + // enable-method = "psci"; |
| 88 | + // clocks = <0x09 0x00>; |
| 89 | + // capacity-dmips-mhz = <0x161c>; |
| 90 | + // phandle = <0x05>; |
| 91 | + // }; |
| 92 | + |
| 93 | + // cpu@101 { |
| 94 | + // device_type = "cpu"; |
| 95 | + // compatible = "phytium,ftc664\0arm,armv8"; |
| 96 | + // reg = <0x00 0x100>; |
| 97 | + // enable-method = "psci"; |
| 98 | + // clocks = <0x09 0x01>; |
| 99 | + // capacity-dmips-mhz = <0x161c>; |
| 100 | + // phandle = <0x06>; |
| 101 | + // }; |
| 102 | + }; |
| 103 | + |
| 104 | + interrupt-controller@30800000 { |
| 105 | + compatible = "arm,gic-v3"; |
| 106 | + #interrupt-cells = <0x03>; |
| 107 | + #address-cells = <0x02>; |
| 108 | + #size-cells = <0x02>; |
| 109 | + ranges; |
| 110 | + interrupt-controller; |
| 111 | + reg = <0x00 0x30800000 0x00 0x20000 0x00 0x30880000 0x00 0x80000 0x00 0x30840000 0x00 0x10000 0x00 0x30850000 0x00 0x10000 0x00 0x30860000 0x00 0x10000>; |
| 112 | + interrupts = <0x01 0x09 0x08>; |
| 113 | + phandle = <0x01>; |
| 114 | + |
| 115 | + gic-its@30820000 { |
| 116 | + compatible = "arm,gic-v3-its"; |
| 117 | + msi-controller; |
| 118 | + reg = <0x00 0x30820000 0x00 0x20000>; |
| 119 | + phandle = <0x0f>; |
| 120 | + }; |
| 121 | + }; |
| 122 | + |
| 123 | + timer { |
| 124 | + compatible = "arm,armv8-timer"; |
| 125 | + interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>; |
| 126 | + clock-frequency = <0x2faf080>; |
| 127 | + }; |
| 128 | + |
| 129 | + soc { |
| 130 | + compatible = "simple-bus"; |
| 131 | + #address-cells = <0x02>; |
| 132 | + #size-cells = <0x02>; |
| 133 | + dma-coherent; |
| 134 | + ranges; |
| 135 | + |
| 136 | + uart@2800d000 { |
| 137 | + compatible = "arm,pl011\0arm,primecell"; |
| 138 | + reg = <0x00 0x2800d000 0x00 0x1000>; |
| 139 | + interrupts = <0x00 0x54 0x04>; |
| 140 | + clocks = <0x0c 0x0c>; |
| 141 | + clock-names = "uartclk\0apb_pclk"; |
| 142 | + status = "okay"; |
| 143 | + }; |
| 144 | + }; |
| 145 | + |
| 146 | + chosen { |
| 147 | + bootargs = "console=ttyAMA1,115200 earlycon=pl011,0x2800d000 root=/dev/sda2 rootfstype=ext4 rootwait rw cma=256m ;"; |
| 148 | + stdout-path = "serial1:115200n8"; |
| 149 | + }; |
| 150 | + |
| 151 | + memory@00 { |
| 152 | + device_type = "memory"; |
| 153 | + reg = <0x20 0x20000000 0x00 0x20000000>; |
| 154 | + }; |
| 155 | +}; |
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