feat: Added driver support for two platform devices. (#259)

* feat: Added driver support for two platform devices.

* fix: fix ci issues

Author: YanLien

Cargo.lock

@@ -14,6 +14,8 @@ ept-level-4 = ["axaddrspace/4-level-ept"]
 fs = ["axstd/fs"]
 
 plat-aarch64-generic = ["axplat-aarch64-generic", "axstd/driver-dyn"]
+plat-aarch64-phytium-pi = ["axplat-aarch64-phytium-pi", "axstd/driver-dyn"]
+plat-aarch64-roc-rk3568-pc = ["axplat-aarch64-roc-rk3568-pc", "axstd/driver-dyn"]
 plat-x86-qemu-q35 = ["axplat-x86-qemu-q35"]
 
 [dependencies]
@@ -28,7 +30,7 @@ spin = "0.9"
 timer_list = "0.1.0"
 
 # System dependent modules provided by ArceOS.
-axstd = {git = "https://github.com/arceos-hypervisor/arceos.git", tag = "hv-0.3.0", features = [
+axstd = {git = "https://github.com/arceos-hypervisor/arceos.git", tag = "hv-0.3.1", features = [
   "alloc-level-1",
   "paging",
   "irq",
@@ -64,6 +66,8 @@ axvisor_api = "0.1"
 # platform
 axplat-aarch64-generic = {path = "platform/aarch64-generic", optional = true}
 axplat-x86-qemu-q35 = {path = "platform/x86-qemu-q35", optional = true}
+axplat-aarch64-phytium-pi = {path = "platform/aarch64-phytium-pi", optional = true}
+axplat-aarch64-roc-rk3568-pc = {path = "platform/aarch64-roc-rk3568-pc", optional = true}
 
 [target.'cfg(target_arch = "aarch64")'.dependencies]
 aarch64-cpu-ext = "0.1"

Cargo.toml

@@ -0,0 +1,11 @@
+[package]
+edition = "2024"
+name = "axplat-aarch64-phytium-pi"
+version = "0.1.0"
+
+[dependencies]
+axbsp-phytium-pi = {git = "https://github.com/drivercraft/axbsp.git", features = ["irq", "smp", "hv"]}
+
+[build-dependencies]
+serde = {version = "1.0", features = ["derive"]}
+toml = "0.8"

platform/aarch64-phytium-pi/Cargo.toml

@@ -0,0 +1,49 @@
+# Architecture identifier.
+arch = "aarch64" # str
+# Platform package.
+package = "axplat-aarch64-phytium-pi" # str
+# Platform identifier.
+platform = "aarch64-phytium-pi" # str
+
+#
+# Device specifications
+#
+[devices]
+# MMIO regions with format (`base_paddr`, `size`).
+mmio-regions = [] # [(uint, uint)]
+# End PCI bus number.
+pci-bus-end = 0 # uint
+# Base physical address of the PCIe ECAM space.
+pci-ecam-base = 0 # uint
+# PCI device memory ranges.
+pci-ranges = [] # [(uint, uint)]
+# Timer interrupt num (PPI, physical timer).
+timer-irq = 26 # uint
+# VirtIO MMIO regions with format (`base_paddr`, `size`).
+virtio-mmio-regions = [] # [(uint, uint)]
+
+#
+# Platform configs
+#
+[plat]
+# Platform family (deprecated).
+family = "" # str
+# Number of CPUs.
+cpu-num = 1                                   # uint
+# No need.
+phys-memory-base = 0                            # uint
+# No need.
+phys-memory-size = 0x0                          # uint
+# No need.
+kernel-base-paddr = 0x0                         # uint
+# Base virtual address of the kernel image.
+kernel-base-vaddr = "0x8000_0000_0000"     # uint
+# No need.
+phys-virt-offset = "0"      # uint
+# Offset of bus address and phys address. some boards, the bus address is
+# different from the physical address.
+phys-bus-offset = 0                             # uint
+# Kernel address space base.
+kernel-aspace-base = "0x0000_0000_0000"    # uint
+# Kernel address space size.
+kernel-aspace-size = "0xffff_ffff_f000"    # uint

platform/aarch64-phytium-pi/axconfig.toml

@@ -0,0 +1,4 @@
+#![no_std]
+#![cfg(target_arch = "aarch64")]
+
+extern crate axbsp_phytium_pi;

platform/aarch64-phytium-pi/src/lib.rs

@@ -0,0 +1,11 @@
+[package]
+edition = "2024"
+name = "axplat-aarch64-roc-rk3568-pc"
+version = "0.1.0"
+
+[dependencies]
+axbsp-roc-rk3568-pc = {git = "https://github.com/drivercraft/axbsp.git", features = ["irq", "smp", "hv"]}
+
+[build-dependencies]
+serde = {version = "1.0", features = ["derive"]}
+toml = "0.8"

platform/aarch64-roc-rk3568-pc/Cargo.toml

@@ -0,0 +1,49 @@
+# Architecture identifier.
+arch = "aarch64" # str
+# Platform package.
+package = "axplat-aarch64-roc-rk3568-pc" # str
+# Platform identifier.
+platform = "aarch64-roc-rk3568-pc" # str
+
+#
+# Device specifications
+#
+[devices]
+# MMIO regions with format (`base_paddr`, `size`).
+mmio-regions = [] # [(uint, uint)]
+# End PCI bus number.
+pci-bus-end = 0 # uint
+# Base physical address of the PCIe ECAM space.
+pci-ecam-base = 0 # uint
+# PCI device memory ranges.
+pci-ranges = [] # [(uint, uint)]
+# Timer interrupt num (PPI, physical timer).
+timer-irq = 26 # uint
+# VirtIO MMIO regions with format (`base_paddr`, `size`).
+virtio-mmio-regions = [] # [(uint, uint)]
+
+#
+# Platform configs
+#
+[plat]
+# Platform family (deprecated).
+family = "" # str
+# Number of CPUs.
+cpu-num = 1                                   # uint
+# No need.
+phys-memory-base = 0                            # uint
+# No need.
+phys-memory-size = 0x0                          # uint
+# No need.
+kernel-base-paddr = 0x0                         # uint
+# Base virtual address of the kernel image.
+kernel-base-vaddr = "0x8000_0000_0000"     # uint
+# No need.
+phys-virt-offset = "0"      # uint
+# Offset of bus address and phys address. some boards, the bus address is
+# different from the physical address.
+phys-bus-offset = 0                             # uint
+# Kernel address space base.
+kernel-aspace-base = "0x0000_0000_0000"    # uint
+# Kernel address space size.
+kernel-aspace-size = "0xffff_ffff_f000"    # uint

platform/aarch64-roc-rk3568-pc/axconfig.toml

@@ -0,0 +1,4 @@
+#![no_std]
+#![cfg(target_arch = "aarch64")]
+
+extern crate axbsp_roc_rk3568_pc;

platform/aarch64-roc-rk3568-pc/src/lib.rs

@@ -10,6 +10,10 @@ extern crate axstd as std;
 
 #[cfg(feature = "plat-aarch64-generic")]
 extern crate axplat_aarch64_generic;
+#[cfg(feature = "plat-aarch64-phytium-pi")]
+extern crate axplat_aarch64_phytium_pi;
+#[cfg(feature = "plat-aarch64-roc-rk3568-pc")]
+extern crate axplat_aarch64_roc_rk3568_pc;
 #[cfg(feature = "plat-x86-qemu-q35")]
 extern crate axplat_x86_qemu_q35;