refactor: deps git to crates-io

Author: ZR233

Cargo.toml

@@ -22,19 +22,20 @@ page_table_multiarch = "0.5"
 percpu = { version = "0.2.0", features = ["arm-el2"] }
 
 # System dependent modules provided by ArceOS-Hypervisor.
-axvcpu = { git = "https://github.com/arceos-hypervisor/axvcpu.git" }
-axaddrspace = { git = "https://github.com/arceos-hypervisor/axaddrspace.git" }
+axvcpu = "0.1"
+axcpu = { version = "0.2", features = ["arm-el2"] }
+axaddrspace = "0.1"
 axdevice = { git = "https://github.com/arceos-hypervisor/axdevice.git" }
-axdevice_base = { git = "https://github.com/arceos-hypervisor/axdevice_crates.git" }
-axvmconfig = { git = "https://github.com/arceos-hypervisor/axvmconfig.git", default-features = false }
+axdevice_base = "0.1"
+axvmconfig = { version = "0.1", default-features = false }
 
 [target.'cfg(target_arch = "x86_64")'.dependencies]
-x86_vcpu = { git = "https://github.com/arceos-hypervisor/x86_vcpu.git" }
+x86_vcpu = "0.1"
 
 [target.'cfg(target_arch = "riscv64")'.dependencies]
-riscv_vcpu = { git = "https://github.com/arceos-hypervisor/riscv_vcpu.git" }
+riscv_vcpu = "0.1"
 
 [target.'cfg(target_arch = "aarch64")'.dependencies]
-arm_vcpu = { git = "https://github.com/arceos-hypervisor/arm_vcpu.git" }
-arm_vgic = { git = "https://github.com/arceos-hypervisor/arm_vgic.git", features = ["vgicv3"] }
+arm_vcpu = { git = "https://github.com/arceos-hypervisor/arm_vcpu", branch = "next-dev" }
+arm_vgic = { version = "0.1", features = ["vgicv3"] }
 

src/vm.rs

@@ -11,7 +11,7 @@ use spin::Mutex;
 
 use axaddrspace::{AddrSpace, GuestPhysAddr, HostPhysAddr, MappingFlags, device::AccessWidth};
 use axdevice::{AxVmDeviceConfig, AxVmDevices};
-use axvcpu::{AxArchVCpu, AxVCpu, AxVCpuExitReason, AxVCpuHal};
+use axvcpu::{AxVCpu, AxVCpuExitReason, AxVCpuHal};
 use cpumask::CpuMask;
 
 use crate::config::{AxVMConfig, VmMemMappingType};
@@ -295,7 +295,7 @@ impl<H: AxVMHal, U: AxVCpuHal> AxVM<H, U> {
                 }
                 #[cfg(not(target_arch = "aarch64"))]
                 {
-                    <AxArchVCpuImpl<U> as AxArchVCpu>::SetupConfig::default()
+                    <AxArchVCpuImpl<U> as axvcpu::AxArchVCpu>::SetupConfig::default()
                 }
             };
 
@@ -435,15 +435,13 @@ impl<H: AxVMHal, U: AxVCpuHal> AxVM<H, U> {
                     reg_width: _,
                     signed_ext: _,
                 } => {
-                    let val = self
-                        .get_devices()
-                        .handle_mmio_read(*addr, (*width).into())?;
+                    let val = self.get_devices().handle_mmio_read(*addr, *width)?;
                     vcpu.set_gpr(*reg, val);
                     true
                 }
                 AxVCpuExitReason::MmioWrite { addr, width, data } => {
                     self.get_devices()
-                        .handle_mmio_write(*addr, (*width).into(), *data as usize)?;
+                        .handle_mmio_write(*addr, *width, *data as usize)?;
                     true
                 }
                 AxVCpuExitReason::IoRead { port, width } => {
@@ -591,7 +589,7 @@ impl<H: AxVMHal, U: AxVCpuHal> AxVM<H, U> {
                     )
                 };
                 let mut copied_bytes = 0;
-                for (_i, chunk) in buffer.iter_mut().enumerate() {
+                for chunk in buffer.iter_mut() {
                     let end = copied_bytes + chunk.len();
                     chunk.copy_from_slice(&bytes[copied_bytes..end]);
                     copied_bytes += chunk.len();