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[feat] introduce AxVcpuAccessGuestState
1 parent 3db7d97 commit fc8850f

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2 files changed

+67
-7
lines changed

2 files changed

+67
-7
lines changed

src/page_table.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -136,10 +136,10 @@ impl<PTE: GenericPTE, H: PagingHandler, EPT: EPTTranslator> GuestPageTable64<PTE
136136
let hpa = EPT::guest_phys_to_host_phys(gpa).unwrap();
137137
let ptr = H::phys_to_virt(hpa).as_ptr() as _;
138138

139-
debug!(
140-
"GuestPageTable64::table_of gpa: {:?} hpa: {:?} ptr: {:p}",
141-
gpa, hpa, ptr
142-
);
139+
// debug!(
140+
// "GuestPageTable64::table_of gpa: {:?} hpa: {:?} ptr: {:p}",
141+
// gpa, hpa, ptr
142+
// );
143143

144144
unsafe { core::slice::from_raw_parts(ptr, ENTRY_COUNT) }
145145
}

src/vmx/vcpu.rs

Lines changed: 63 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ use page_table_multiarch::{PageSize, PagingHandler, PagingResult};
1717
use axaddrspace::EPTTranslator;
1818
use axaddrspace::{GuestPhysAddr, GuestVirtAddr, HostPhysAddr, MappingFlags, NestedPageFaultInfo};
1919
use axerrno::{AxResult, ax_err, ax_err_type};
20-
use axvcpu::{AccessWidth, AxArchVCpu, AxVCpuExitReason, AxVCpuHal};
20+
use axvcpu::{AccessWidth, AxArchVCpu, AxVCpuExitReason, AxVCpuHal, AxVcpuAccessGuestState};
2121

2222
use super::VmxExitInfo;
2323
use super::as_axerr;
@@ -793,13 +793,13 @@ impl<H: AxVCpuHal> VmxVcpu<H> {
793793
vaddr + seg_base
794794
}
795795

796-
fn guest_page_table_query(
796+
pub fn guest_page_table_query(
797797
&self,
798798
gva: GuestVirtAddr,
799799
) -> PagingResult<(GuestPhysAddr, MappingFlags, PageSize)> {
800800
let addr = self.gva_to_linear_addr(gva);
801801

802-
debug!("guest_page_table_query: gva {:?} linear {:?}", gva, addr);
802+
// debug!("guest_page_table_query: gva {:?} linear {:?}", gva, addr);
803803

804804
let guest_ptw_info = self.get_pagetable_walk_info();
805805
let guest_page_table: GuestPageTable64<X64PTE, H::PagingHandler, H::EPTTranslator> =
@@ -1367,3 +1367,63 @@ impl<H: AxVCpuHal> AxArchVCpu for VmxVcpu<H> {
13671367
self.regs_mut().set_reg_of_index(reg as u8, val as u64);
13681368
}
13691369
}
1370+
1371+
impl<H: AxVCpuHal> AxVcpuAccessGuestState for VmxVcpu<H> {
1372+
fn read_gpr(&self, reg: usize) -> usize {
1373+
self.regs().get_reg_of_index(reg as u8) as usize
1374+
}
1375+
1376+
fn write_gpr(&mut self, reg: usize, val: usize) {
1377+
self.regs_mut().set_reg_of_index(reg as u8, val as u64);
1378+
}
1379+
1380+
fn instr_pointer(&self) -> usize {
1381+
VmcsGuestNW::RIP.read().expect("Failed to read RIP") as usize
1382+
}
1383+
1384+
fn set_instr_pointer(&mut self, val: usize) {
1385+
VmcsGuestNW::RIP.write(val as _).expect("Failed to set RIP");
1386+
}
1387+
1388+
fn stack_pointer(&self) -> usize {
1389+
self.stack_pointer()
1390+
}
1391+
1392+
fn set_stack_pointer(&mut self, val: usize) {
1393+
self.set_stack_pointer(val);
1394+
}
1395+
1396+
fn frame_pointer(&self) -> usize {
1397+
self.regs().rbp as usize
1398+
}
1399+
1400+
fn set_frame_pointer(&mut self, val: usize) {
1401+
self.regs_mut().rbp = val as u64;
1402+
}
1403+
1404+
fn return_value(&self) -> usize {
1405+
self.regs().rax as usize
1406+
}
1407+
1408+
fn set_return_value(&mut self, val: usize) {
1409+
self.regs_mut().rax = val as u64;
1410+
}
1411+
1412+
fn guest_is_privileged(&self) -> bool {
1413+
use crate::segmentation::SegmentAccessRights;
1414+
SegmentAccessRights::from_bits_truncate(
1415+
VmcsGuest32::CS_ACCESS_RIGHTS
1416+
.read()
1417+
.expect("Failed to read CS_ACCESS_RIGHTS"),
1418+
)
1419+
.dpl()
1420+
== 0
1421+
}
1422+
1423+
fn guest_page_table_query(
1424+
&self,
1425+
gva: GuestVirtAddr,
1426+
) -> Option<(GuestPhysAddr, MappingFlags, PageSize)> {
1427+
self.guest_page_table_query(gva).ok()
1428+
}
1429+
}

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