11# Architecture identifier.
2- arch = " riscv64 " # str
3- # Platform package .
4- package = " axplat-riscv64-qemu-virt " # str
2+ arch = " x86_64 " # str
3+ # Platform Package .
4+ package = " axplat-x86-pc " # str
55# Platform identifier.
6- platform = " riscv64-qemu-virt " # str
6+ platform = " x86-pc " # str
77# Stack size of each task.
88task-stack-size = 0x40000 # uint
99# Number of timer ticks per second (Hz). A timer tick may contain several timer
@@ -15,68 +15,28 @@ ticks-per-sec = 100 # uint
1515#
1616[devices ]
1717# IPI interrupt num
18- ipi-irq = " 0x8000_0000_0000_0001 " # uint
18+ ipi-irq = 0xf3 # uint
1919# MMIO ranges with format (`base_paddr`, `size`).
2020mmio-ranges = [
21- [0x0010_1000 , 0x1000 ],
22- [0x0c00_0000 , 0x21_0000 ],
23- [0x1000_0000 , 0x1000 ],
24- [0x1000_1000 , 0x8000 ],
25- [0x2000_0000 , 0x400_0000 ],
26- [0x3000_0000 , 0x1000_0000 ],
27- [0x4000_0000 , 0x4000_0000 ]
21+ [0xb000_0000 , 0x1000_0000 ],
22+ [0xfe00_0000 , 0xc0_0000 ],
23+ [0xfec0_0000 , 0x1000 ],
24+ [0xfed0_0000 , 0x1000 ],
25+ [0xfee0_0000 , 0x1000 ],
26+ [0xFFC0_0000 , 0x40_0000 ]
2827] # [(uint, uint)]
29- # End PCI bus number (`bus-range` property in device tree) .
28+ # End PCI bus number.
3029pci-bus-end = 0xff # uint
31- # Base physical address of the PCIe ECAM space.
32- pci-ecam-base = 0x3000_0000 # uint
33- # PCI device memory ranges (`ranges` property in device tree).
34- pci-ranges = [
35- [0x0300_0000 , 0x1_0000 ],
36- [0x4000_0000 , 0x4000_0000 ],
37- [0x4_0000_0000 , 0x4_0000_0000 ]
38- ] # [(uint, uint)]
39- # plic@c000000 {
40- # phandle = <0x03>;
41- # riscv,ndev = <0x5f>;
42- # reg = <0x00 0xc000000 0x00 0x600000>;
43- # interrupts-extended = <0x02 0x0b 0x02 0x09>;
44- # interrupt-controller;
45- # compatible = "sifive,plic-1.0.0\0riscv,plic0";
46- # };
47- plic-paddr = 0x0c00_0000 # uint
48- # rtc@101000 {
49- # interrupts = <0x0b>;
50- # interrupt-parent = <0x03>;
51- # reg = <0x00 0x101000 0x00 0x1000>;
52- # compatible = "google,goldfish-rtc";
53- # };
54- # RTC (goldfish) Address
55- rtc-paddr = 0x10_1000 # uint
56- # Timer interrupt frequency in Hz.
57- timer-frequency = 10_000_000 # uint
30+ # Base physical address of the PCIe ECAM space (should read from ACPI 'MCFG' table).
31+ pci-ecam-base = 0xb000_0000 # uint
32+ # PCI device memory ranges (not used on x86).
33+ pci-ranges = [] # [(uint, uint)]
34+ # Timer interrupt frequency in Hz. (4.0GHz)
35+ timer-frequency = 4_000_000_000 # uint
5836# Timer interrupt num.
59- timer-irq = " 0x8000_0000_0000_0005" # uint
60- uart-irq = 0x0a # uint
61- # serial@10000000 {
62- # interrupts = <0x0a>;
63- # interrupt-parent = <0x03>;
64- # clock-frequency = "\08@";
65- # reg = <0x00 0x10000000 0x00 0x100>;
66- # compatible = "ns16550a";
67- # };
68- uart-paddr = 0x1000_0000 # uint
37+ timer-irq = 0xf0 # uint
6938# VirtIO MMIO ranges with format (`base_paddr`, `size`).
70- virtio-mmio-ranges = [
71- [0x1000_1000 , 0x1000 ],
72- [0x1000_2000 , 0x1000 ],
73- [0x1000_3000 , 0x1000 ],
74- [0x1000_4000 , 0x1000 ],
75- [0x1000_5000 , 0x1000 ],
76- [0x1000_6000 , 0x1000 ],
77- [0x1000_7000 , 0x1000 ],
78- [0x1000_8000 , 0x1000 ]
79- ] # [(uint, uint)]
39+ virtio-mmio-ranges = [] # [(uint, uint)]
8040
8141#
8242# Platform configs
@@ -85,22 +45,22 @@ virtio-mmio-ranges = [
8545# Stack size on bootstrapping. (256K)
8646boot-stack-size = 0x40000 # uint
8747# Number of CPUs.
88- cpu-num = 1 # uint
48+ max- cpu-num = 1 # uint
8949# Kernel address space base.
90- kernel-aspace-base = " 0xffff_ffc0_0000_0000 " # uint
50+ kernel-aspace-base = " 0xffff_8000_0000_0000 " # uint
9151# Kernel address space size.
92- kernel-aspace-size = " 0x0000_003f_ffff_f000 " # uint
52+ kernel-aspace-size = " 0x0000_7fff_ffff_f000 " # uint
9353# Base physical address of the kernel image.
94- kernel-base-paddr = 0x8020_0000 # uint
54+ kernel-base-paddr = 0x20_0000 # uint
9555# Base virtual address of the kernel image.
96- kernel-base-vaddr = " 0xffff_ffc0_8020_0000 " # uint
56+ kernel-base-vaddr = " 0xffff_8000_0020_0000 " # uint
9757# Offset of bus address and phys address. some boards, the bus address is
9858# different from the physical address.
9959phys-bus-offset = 0 # uint
10060# Base address of the whole physical memory.
101- phys-memory-base = 0x8000_0000 # uint
61+ phys-memory-base = 0 # uint
10262# Size of the whole physical memory. (128M)
10363phys-memory-size = 0x800_0000 # uint
10464# Linear mapping offset, for quick conversions between physical and virtual
10565# addresses.
106- phys-virt-offset = " 0xffff_ffc0_0000_0000 " # uint
66+ phys-virt-offset = " 0xffff_8000_0000_0000 " # uint
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