11# Architecture identifier.
2- arch = " riscv64 " # str
3- # Platform package .
4- package = " axplat-riscv64-qemu-virt " # str
2+ arch = " x86_64 " # str
3+ # Platform Package .
4+ package = " axplat-x86-pc " # str
55# Platform identifier.
6- platform = " riscv64-qemu-virt " # str
6+ platform = " x86-pc " # str
77# Stack size of each task.
88task-stack-size = 0x40000 # uint
99# Number of timer ticks per second (Hz). A timer tick may contain several timer
@@ -15,67 +15,27 @@ ticks-per-sec = 100 # uint
1515#
1616[devices ]
1717# IPI interrupt num
18- ipi-irq = " 0x8000_0000_0000_0001 " # uint
18+ ipi-irq = 0xf3 # uint
1919# MMIO ranges with format (`base_paddr`, `size`).
2020mmio-ranges = [
21- [0x0010_1000 , 0x1000 ],
22- [0x0c00_0000 , 0x21_0000 ],
23- [0x1000_0000 , 0x1000 ],
24- [0x1000_1000 , 0x8000 ],
25- [0x3000_0000 , 0x1000_0000 ],
26- [0x4000_0000 , 0x4000_0000 ]
21+ [0xb000_0000 , 0x1000_0000 ],
22+ [0xfe00_0000 , 0xc0_0000 ],
23+ [0xfec0_0000 , 0x1000 ],
24+ [0xfed0_0000 , 0x1000 ],
25+ [0xfee0_0000 , 0x1000 ]
2726] # [(uint, uint)]
28- # End PCI bus number (`bus-range` property in device tree) .
27+ # End PCI bus number.
2928pci-bus-end = 0xff # uint
30- # Base physical address of the PCIe ECAM space.
31- pci-ecam-base = 0x3000_0000 # uint
32- # PCI device memory ranges (`ranges` property in device tree).
33- pci-ranges = [
34- [0x0300_0000 , 0x1_0000 ],
35- [0x4000_0000 , 0x4000_0000 ],
36- [0x4_0000_0000 , 0x4_0000_0000 ]
37- ] # [(uint, uint)]
38- # plic@c000000 {
39- # phandle = <0x03>;
40- # riscv,ndev = <0x5f>;
41- # reg = <0x00 0xc000000 0x00 0x600000>;
42- # interrupts-extended = <0x02 0x0b 0x02 0x09>;
43- # interrupt-controller;
44- # compatible = "sifive,plic-1.0.0\0riscv,plic0";
45- # };
46- plic-paddr = 0x0c00_0000 # uint
47- # rtc@101000 {
48- # interrupts = <0x0b>;
49- # interrupt-parent = <0x03>;
50- # reg = <0x00 0x101000 0x00 0x1000>;
51- # compatible = "google,goldfish-rtc";
52- # };
53- # RTC (goldfish) Address
54- rtc-paddr = 0x10_1000 # uint
55- # Timer interrupt frequency in Hz.
56- timer-frequency = 10_000_000 # uint
29+ # Base physical address of the PCIe ECAM space (should read from ACPI 'MCFG' table).
30+ pci-ecam-base = 0xb000_0000 # uint
31+ # PCI device memory ranges (not used on x86).
32+ pci-ranges = [] # [(uint, uint)]
33+ # Timer interrupt frequency in Hz. (4.0GHz)
34+ timer-frequency = 4_000_000_000 # uint
5735# Timer interrupt num.
58- timer-irq = " 0x8000_0000_0000_0005" # uint
59- uart-irq = 0x0a # uint
60- # serial@10000000 {
61- # interrupts = <0x0a>;
62- # interrupt-parent = <0x03>;
63- # clock-frequency = "\08@";
64- # reg = <0x00 0x10000000 0x00 0x100>;
65- # compatible = "ns16550a";
66- # };
67- uart-paddr = 0x1000_0000 # uint
36+ timer-irq = 0xf0 # uint
6837# VirtIO MMIO ranges with format (`base_paddr`, `size`).
69- virtio-mmio-ranges = [
70- [0x1000_1000 , 0x1000 ],
71- [0x1000_2000 , 0x1000 ],
72- [0x1000_3000 , 0x1000 ],
73- [0x1000_4000 , 0x1000 ],
74- [0x1000_5000 , 0x1000 ],
75- [0x1000_6000 , 0x1000 ],
76- [0x1000_7000 , 0x1000 ],
77- [0x1000_8000 , 0x1000 ]
78- ] # [(uint, uint)]
38+ virtio-mmio-ranges = [] # [(uint, uint)]
7939
8040#
8141# Platform configs
@@ -86,20 +46,20 @@ boot-stack-size = 0x40000 # uint
8646# Number of CPUs.
8747cpu-num = 1 # uint
8848# Kernel address space base.
89- kernel-aspace-base = " 0xffff_ffc0_0000_0000 " # uint
49+ kernel-aspace-base = " 0xffff_8000_0000_0000 " # uint
9050# Kernel address space size.
91- kernel-aspace-size = " 0x0000_003f_ffff_f000 " # uint
51+ kernel-aspace-size = " 0x0000_7fff_ffff_f000 " # uint
9252# Base physical address of the kernel image.
93- kernel-base-paddr = 0x8020_0000 # uint
53+ kernel-base-paddr = 0x20_0000 # uint
9454# Base virtual address of the kernel image.
95- kernel-base-vaddr = " 0xffff_ffc0_8020_0000 " # uint
55+ kernel-base-vaddr = " 0xffff_8000_0020_0000 " # uint
9656# Offset of bus address and phys address. some boards, the bus address is
9757# different from the physical address.
9858phys-bus-offset = 0 # uint
9959# Base address of the whole physical memory.
100- phys-memory-base = 0x8000_0000 # uint
60+ phys-memory-base = 0 # uint
10161# Size of the whole physical memory. (128M)
10262phys-memory-size = 0x800_0000 # uint
10363# Linear mapping offset, for quick conversions between physical and virtual
10464# addresses.
105- phys-virt-offset = " 0xffff_ffc0_0000_0000 " # uint
65+ phys-virt-offset = " 0xffff_8000_0000_0000 " # uint
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