Bump to v0.5.5

Author: equation314

CHANGELOG.md

@@ -1,8 +1,14 @@
 # Changelog
 
+## 0.5.5
+
+### Bug Fixes
+
+- [Fix memory leak in `PageTable64::dealloc_tree`](https://github.com/arceos-org/page_table_multiarch/pull/22).
+
 ## 0.5.4
 
-## New Features
+### New Features
 
 - [Fix invalid query result](https://github.com/arceos-org/page_table_multiarch/pull/17).
 - [Fix incorrect TLB flush VA bits on aarch64](https://github.com/arceos-org/page_table_multiarch/pull/21).

Cargo.lock

@@ -4,7 +4,7 @@ resolver = "2"
 members = ["page_table_multiarch", "page_table_entry"]
 
 [workspace.package]
-version = "0.5.4"
+version = "0.5.5"
 edition = "2024"
 authors = ["Yuekai Jia <[email protected]>"]
 license = "GPL-3.0-or-later OR Apache-2.0 OR MulanPSL-2.0"

Cargo.toml

@@ -5,12 +5,10 @@ use page_table_entry::riscv::Rv64PTE;
 
 #[inline]
 fn riscv_flush_tlb(vaddr: Option<memory_addr::VirtAddr>) {
-    unsafe {
-        if let Some(vaddr) = vaddr {
-            riscv::asm::sfence_vma(0, vaddr.as_usize())
-        } else {
-            riscv::asm::sfence_vma_all();
-        }
+    if let Some(vaddr) = vaddr {
+        riscv::asm::sfence_vma(0, vaddr.as_usize())
+    } else {
+        riscv::asm::sfence_vma_all();
     }
 }
 

page_table_multiarch/src/arch/riscv.rs

@@ -200,10 +200,7 @@ impl<M: PagingMetaData, PTE: GenericPTE, H: PagingHandler> PageTable64<M, PTE, H
                 PageSize::Size4K
             };
             let tlb = self.map(vaddr, paddr, page_size, flags).inspect_err(|e| {
-                error!(
-                    "failed to map page: {:#x?}({:?}) -> {:#x?}, {:?}",
-                    vaddr_usize, page_size, paddr, e
-                )
+                error!("failed to map page: {vaddr_usize:#x?}({page_size:?}) -> {paddr:#x?}, {e:?}")
             })?;
             if flush_tlb_by_page {
                 M::flush_tlb(Some(vaddr));
@@ -245,7 +242,7 @@ impl<M: PagingMetaData, PTE: GenericPTE, H: PagingHandler> PageTable64<M, PTE, H
             let vaddr = vaddr_usize.into();
             let (_, page_size, tlb) = self
                 .unmap(vaddr)
-                .inspect_err(|e| error!("failed to unmap page: {:#x?}, {:?}", vaddr_usize, e))?;
+                .inspect_err(|e| error!("failed to unmap page: {vaddr_usize:#x?}, {e:?}"))?;
             if flush_tlb_by_page {
                 tlb.flush();
             } else {
@@ -287,7 +284,7 @@ impl<M: PagingMetaData, PTE: GenericPTE, H: PagingHandler> PageTable64<M, PTE, H
             let vaddr = vaddr_usize.into();
             let (page_size, tlb) = self
                 .protect(vaddr, flags)
-                .inspect_err(|e| error!("failed to protect page: {:#x?}, {:?}", vaddr_usize, e))?;
+                .inspect_err(|e| error!("failed to protect page: {vaddr_usize:#x?}, {e:?}"))?;
             if flush_tlb_by_page {
                 tlb.flush();
             } else {

page_table_multiarch/src/bits64.rs

@@ -15,7 +15,9 @@ const PAGE_LAYOUT: Layout = unsafe { Layout::from_size_align_unchecked(4096, 409
 thread_local! {
     static ALLOCATED: RefCell<HashSet<usize>> = RefCell::default();
 }
+
 struct TrackPagingHandler<M: PagingMetaData>(PhantomData<M>);
+
 impl<M: PagingMetaData> PagingHandler for TrackPagingHandler<M> {
     fn alloc_frame() -> Option<PhysAddr> {
         let ptr = unsafe { alloc::alloc(PAGE_LAYOUT) } as usize;
@@ -38,9 +40,7 @@ impl<M: PagingMetaData> PagingHandler for TrackPagingHandler<M> {
     }
 
     fn phys_to_virt(paddr: PhysAddr) -> VirtAddr {
-        if paddr.as_usize() == 0 {
-            panic!();
-        }
+        assert!(paddr.as_usize() > 0);
         VirtAddr::from_usize(paddr.as_usize())
     }
 }
@@ -91,36 +91,41 @@ fn run_test_for<M: PagingMetaData<VirtAddr = VirtAddr>, PTE: GenericPTE>() -> Pa
 }
 
 #[test]
-fn test_dealloc() -> PagingResult<()> {
-    #[cfg(target_arch = "x86_64")]
+fn test_dealloc_x86() -> PagingResult<()> {
     run_test_for::<
         page_table_multiarch::x86_64::X64PagingMetaData,
         page_table_entry::x86_64::X64PTE,
     >()?;
+    Ok(())
+}
 
-    #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
-    {
-        run_test_for::<
-            page_table_multiarch::riscv::Sv39MetaData<VirtAddr>,
-            page_table_entry::riscv::Rv64PTE,
-        >()?;
-        run_test_for::<
-            page_table_multiarch::riscv::Sv48MetaData<VirtAddr>,
-            page_table_entry::riscv::Rv64PTE,
-        >()?;
-    }
+#[test]
+fn test_dealloc_riscv() -> PagingResult<()> {
+    run_test_for::<
+        page_table_multiarch::riscv::Sv39MetaData<VirtAddr>,
+        page_table_entry::riscv::Rv64PTE,
+    >()?;
+    run_test_for::<
+        page_table_multiarch::riscv::Sv48MetaData<VirtAddr>,
+        page_table_entry::riscv::Rv64PTE,
+    >()?;
+    Ok(())
+}
 
-    #[cfg(target_arch = "aarch64")]
+#[test]
+fn test_dealloc_aarch64() -> PagingResult<()> {
     run_test_for::<
         page_table_multiarch::aarch64::A64PagingMetaData,
         page_table_entry::aarch64::A64PTE,
     >()?;
+    Ok(())
+}
 
-    #[cfg(target_arch = "loongarch64")]
+#[test]
+fn test_dealloc_loongarch64() -> PagingResult<()> {
     run_test_for::<
         page_table_multiarch::loongarch64::LA64MetaData,
         page_table_entry::loongarch64::LA64PTE,
     >()?;
-
     Ok(())
 }