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fix: remove target-specific crates for page_table_multiarch/all
1 parent e3294fb commit a935131

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4 files changed

+12
-7
lines changed

4 files changed

+12
-7
lines changed

page_table_entry/Cargo.toml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -23,13 +23,13 @@ memory_addr.workspace = true
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# Target-specific dependencies
2525
aarch64-cpu = { version = "10.0", optional = true }
26-
x86_64 = { version = "0.15", optional = true }
26+
x86_64 = { version = "0.15", default-features = false, optional = true }
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[target.'cfg(target_arch = "aarch64")'.dependencies]
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aarch64-cpu = "10.0"
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[target.'cfg(target_arch = "x86_64")'.dependencies]
32-
x86_64 = "0.15"
32+
x86_64 = { version = "0.15", default-features = false }
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[package.metadata.docs.rs]
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all-features = true

page_table_multiarch/Cargo.toml

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ rust-version.workspace = true
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default = []
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copy-from = ["dep:bitmaps"]
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19-
all = ["page_table_entry/all", "dep:riscv", "dep:x86_64"]
19+
all = ["page_table_entry/all"]
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2121
[dependencies]
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log = "0.4"
@@ -25,11 +25,10 @@ page_table_entry.workspace = true
2525
bitmaps = { version = "3.2", default-features = false, optional = true }
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# Target-specific dependencies
28-
riscv = { version = "0.14", default-features = false, optional = true }
29-
x86_64 = { version = "0.15", optional = true }
30-
3128
[target.'cfg(target_arch = "x86_64")'.dependencies]
32-
x86_64 = "0.15"
29+
x86_64 = { version = "0.15", default-features = false, features = [
30+
"instructions",
31+
] }
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[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
3534
riscv = { version = "0.14", default-features = false }

page_table_multiarch/src/arch/riscv.rs

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,11 +12,14 @@ pub trait SvVirtAddr: memory_addr::MemoryAddr + Send + Sync {
1212
impl SvVirtAddr for memory_addr::VirtAddr {
1313
#[inline]
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fn flush_tlb(vaddr: Option<Self>) {
15+
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
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if let Some(vaddr) = vaddr {
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riscv::asm::sfence_vma(0, vaddr.as_usize())
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} else {
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riscv::asm::sfence_vma_all();
1920
}
21+
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
22+
let _ = vaddr;
2023
}
2124
}
2225

page_table_multiarch/src/arch/x86_64.rs

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,11 +14,14 @@ impl PagingMetaData for X64PagingMetaData {
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#[inline]
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fn flush_tlb(vaddr: Option<memory_addr::VirtAddr>) {
17+
#[cfg(target_arch = "x86_64")]
1718
if let Some(vaddr) = vaddr {
1819
x86_64::instructions::tlb::flush(x86_64::VirtAddr::new(vaddr.as_usize() as u64));
1920
} else {
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x86_64::instructions::tlb::flush_all();
2122
}
23+
#[cfg(not(target_arch = "x86_64"))]
24+
let _ = vaddr;
2225
}
2326
}
2427

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