tlb flush support smp

Signed-off-by: Weikang Guo <guoweikang@kylinos.cn>

Author: guoweikang

page_table_multiarch/src/arch/aarch64.rs

@@ -23,14 +23,15 @@ impl PagingMetaData for A64PagingMetaData {
 
     #[inline]
     fn flush_tlb(vaddr: Option<VirtAddr>) {
+        // make sure all previous page table writes are visible
         unsafe {
             if let Some(vaddr) = vaddr {
                 // TLB Invalidate by VA, All ASID, EL1, Inner Shareable
                 const VA_MASK: usize = (1 << 44) - 1; // VA[55:12] => bits[43:0]
-                asm!("tlbi vaae1is, {}; dsb sy; isb", in(reg) ((vaddr.as_usize() >> 12) & VA_MASK))
+                asm!("dsb ishst; tlbi vaae1is, {}; dsb ish; isb", in(reg) ((vaddr.as_usize() >> 12) & VA_MASK))
             } else {
                 // TLB Invalidate by VMID, All at stage 1, EL1
-                asm!("tlbi vmalle1; dsb sy; isb")
+                asm!("dsb ishst; tlbi vmalle1is; dsb ish; isb")
             }
         }
     }