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AsakuraMizuAsakuraMizu
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feat: add all feature for doc and test
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-72
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12 files changed

+116
-72
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‎.github/workflows/ci.yml‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -27,9 +27,7 @@ jobs:
2727
run: cargo build --target ${{ matrix.targets }} --all-features
2828
- name: Unit test
2929
if: ${{ matrix.targets == 'x86_64-unknown-linux-gnu' }}
30-
env:
31-
RUSTFLAGS: --cfg doc
32-
run: cargo test --target ${{ matrix.targets }} -- --nocapture
30+
run: cargo test --target ${{ matrix.targets }} --all-features -- --nocapture
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3432
doc:
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runs-on: ubuntu-latest
@@ -39,13 +37,11 @@ jobs:
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contents: write
4038
env:
4139
default-branch: ${{ format('refs/heads/{0}', github.event.repository.default_branch) }}
42-
RUSTFLAGS: --cfg doc
4340
RUSTDOCFLAGS: -Zunstable-options --enable-index-page -D rustdoc::broken_intra_doc_links -D missing-docs
4441
steps:
4542
- uses: actions/checkout@v4
4643
- uses: dtolnay/rust-toolchain@nightly
4744
- name: Build docs
48-
continue-on-error: ${{ github.ref != env.default-branch && github.event_name != 'pull_request' }}
4945
run: cargo doc --no-deps --all-features
5046
- name: Deploy to Github Pages
5147
if: ${{ github.ref == env.default-branch }}

‎Cargo.lock‎

Lines changed: 0 additions & 25 deletions
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‎page_table_entry/Cargo.toml‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -15,15 +15,14 @@ rust-version.workspace = true
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[features]
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arm-el2 = []
1717

18+
all = []
19+
1820
[dependencies]
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bitflags = "2.9"
2022
memory_addr.workspace = true
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22-
[target.'cfg(any(target_arch = "aarch64", doc))'.dependencies]
24+
[dev-dependencies]
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aarch64-cpu = "10.0"
2426

25-
[target.'cfg(any(target_arch = "x86_64", doc))'.dependencies]
26-
x86_64 = "0.15.2"
27-
2827
[package.metadata.docs.rs]
29-
rustc-args = ["--cfg", "doc"]
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all-features = true

‎page_table_entry/README.md‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,6 @@ methods for manipulating various page table entries.
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2828
```rust
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use memory_addr::PhysAddr;
30-
use x86_64::structures::paging::page_table::PageTableFlags;
3130
use page_table_entry::{GenericPTE, MappingFlags, x86_64::X64PTE};
3231

3332
let paddr = PhysAddr::from(0x233000);

‎page_table_entry/src/arch/aarch64.rs‎

Lines changed: 14 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
11
//! AArch64 VMSAv8-64 translation table format descriptors.
22
3-
use aarch64_cpu::registers::MAIR_EL1;
43
use core::fmt;
54
use memory_addr::PhysAddr;
65

@@ -99,16 +98,20 @@ impl DescriptorAttr {
9998
impl MemAttr {
10099
/// The MAIR_ELx register should be set to this value to match the memory
101100
/// attributes in the descriptors.
102-
pub const MAIR_VALUE: u64 = {
103-
// Device-nGnRE memory
104-
let attr0 = MAIR_EL1::Attr0_Device::nonGathering_nonReordering_EarlyWriteAck.value;
105-
// Normal memory
106-
let attr1 = MAIR_EL1::Attr1_Normal_Inner::WriteBack_NonTransient_ReadWriteAlloc.value
107-
| MAIR_EL1::Attr1_Normal_Outer::WriteBack_NonTransient_ReadWriteAlloc.value;
108-
let attr2 = MAIR_EL1::Attr2_Normal_Inner::NonCacheable.value
109-
+ MAIR_EL1::Attr2_Normal_Outer::NonCacheable.value;
110-
attr0 | attr1 | attr2 // 0x44_ff_04
111-
};
101+
///
102+
/// ```
103+
/// # use aarch64_cpu::registers::MAIR_EL1;
104+
/// # use page_table_entry::aarch64::MemAttr;
105+
/// // Device-nGnRE memory
106+
/// let attr0 = MAIR_EL1::Attr0_Device::nonGathering_nonReordering_EarlyWriteAck.value;
107+
/// // Normal memory
108+
/// let attr1 = MAIR_EL1::Attr1_Normal_Inner::WriteBack_NonTransient_ReadWriteAlloc.value
109+
/// | MAIR_EL1::Attr1_Normal_Outer::WriteBack_NonTransient_ReadWriteAlloc.value;
110+
/// let attr2 = MAIR_EL1::Attr2_Normal_Inner::NonCacheable.value
111+
/// + MAIR_EL1::Attr2_Normal_Outer::NonCacheable.value;
112+
/// assert_eq!(MemAttr::MAIR_VALUE, attr0 | attr1 | attr2);
113+
/// ```
114+
pub const MAIR_VALUE: u64 = 0x44_ff_04;
112115
}
113116

114117
impl From<DescriptorAttr> for MappingFlags {

‎page_table_entry/src/arch/mod.rs‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
1-
#[cfg(any(target_arch = "x86_64", doc))]
1+
#[cfg(any(target_arch = "x86_64", feature = "all"))]
22
pub mod x86_64;
33

4-
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))]
4+
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", feature = "all"))]
55
pub mod riscv;
66

7-
#[cfg(any(target_arch = "aarch64", doc))]
7+
#[cfg(any(target_arch = "aarch64", feature = "all"))]
88
pub mod aarch64;
99

10-
#[cfg(any(target_arch = "loongarch64", doc))]
10+
#[cfg(any(target_arch = "loongarch64", feature = "all"))]
1111
pub mod loongarch64;

‎page_table_entry/src/arch/x86_64.rs‎

Lines changed: 67 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,10 +3,75 @@
33
use core::fmt;
44
use memory_addr::PhysAddr;
55

6-
pub use x86_64::structures::paging::page_table::PageTableFlags as PTF;
7-
86
use crate::{GenericPTE, MappingFlags};
97

8+
bitflags::bitflags! {
9+
/// Possible flags for a page table entry.
10+
///
11+
/// Reference: https://docs.rs/crate/x86_64/0.15.2/source/src/structures/paging/page_table.rs
12+
#[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
13+
pub struct PTF: u64 {
14+
/// Specifies whether the mapped frame or page table is loaded in memory.
15+
const PRESENT = 1;
16+
/// Controls whether writes to the mapped frames are allowed.
17+
///
18+
/// If this bit is unset in a level 1 page table entry, the mapped frame is read-only.
19+
/// If this bit is unset in a higher level page table entry the complete range of mapped
20+
/// pages is read-only.
21+
const WRITABLE = 1 << 1;
22+
/// Controls whether accesses from userspace (i.e. ring 3) are permitted.
23+
const USER_ACCESSIBLE = 1 << 2;
24+
/// If this bit is set, a “write-through” policy is used for the cache, else a “write-back”
25+
/// policy is used.
26+
const WRITE_THROUGH = 1 << 3;
27+
/// Disables caching for the pointed entry is cacheable.
28+
const NO_CACHE = 1 << 4;
29+
/// Set by the CPU when the mapped frame or page table is accessed.
30+
const ACCESSED = 1 << 5;
31+
/// Set by the CPU on a write to the mapped frame.
32+
const DIRTY = 1 << 6;
33+
/// Specifies that the entry maps a huge frame instead of a page table. Only allowed in
34+
/// P2 or P3 tables.
35+
const HUGE_PAGE = 1 << 7;
36+
/// Indicates that the mapping is present in all address spaces, so it isn't flushed from
37+
/// the TLB on an address space switch.
38+
const GLOBAL = 1 << 8;
39+
/// Available to the OS, can be used to store additional data, e.g. custom flags.
40+
const BIT_9 = 1 << 9;
41+
/// Available to the OS, can be used to store additional data, e.g. custom flags.
42+
const BIT_10 = 1 << 10;
43+
/// Available to the OS, can be used to store additional data, e.g. custom flags.
44+
const BIT_11 = 1 << 11;
45+
/// Available to the OS, can be used to store additional data, e.g. custom flags.
46+
const BIT_52 = 1 << 52;
47+
/// Available to the OS, can be used to store additional data, e.g. custom flags.
48+
const BIT_53 = 1 << 53;
49+
/// Available to the OS, can be used to store additional data, e.g. custom flags.
50+
const BIT_54 = 1 << 54;
51+
/// Available to the OS, can be used to store additional data, e.g. custom flags.
52+
const BIT_55 = 1 << 55;
53+
/// Available to the OS, can be used to store additional data, e.g. custom flags.
54+
const BIT_56 = 1 << 56;
55+
/// Available to the OS, can be used to store additional data, e.g. custom flags.
56+
const BIT_57 = 1 << 57;
57+
/// Available to the OS, can be used to store additional data, e.g. custom flags.
58+
const BIT_58 = 1 << 58;
59+
/// Available to the OS, can be used to store additional data, e.g. custom flags.
60+
const BIT_59 = 1 << 59;
61+
/// Available to the OS, can be used to store additional data, e.g. custom flags.
62+
const BIT_60 = 1 << 60;
63+
/// Available to the OS, can be used to store additional data, e.g. custom flags.
64+
const BIT_61 = 1 << 61;
65+
/// Available to the OS, can be used to store additional data, e.g. custom flags.
66+
const BIT_62 = 1 << 62;
67+
/// Forbid code execution from the mapped frames.
68+
///
69+
/// Can be only used when the no-execute page protection feature is enabled in the EFER
70+
/// register.
71+
const NO_EXECUTE = 1 << 63;
72+
}
73+
}
74+
1075
impl From<PTF> for MappingFlags {
1176
fn from(f: PTF) -> Self {
1277
if !f.contains(PTF::PRESENT) {

‎page_table_multiarch/Cargo.toml‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -16,20 +16,22 @@ rust-version.workspace = true
1616
default = []
1717
copy-from = ["dep:bitmaps"]
1818

19+
all = ["page_table_entry/all"]
20+
1921
[dependencies]
2022
log = "0.4"
2123
memory_addr.workspace = true
2224
page_table_entry.workspace = true
2325
bitmaps = { version = "3.2", default-features = false, optional = true }
2426

25-
[target.'cfg(any(target_arch = "x86_64", doc))'.dependencies]
27+
[target.'cfg(target_arch = "x86_64")'.dependencies]
2628
x86 = "0.52"
2729

28-
[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))'.dependencies]
30+
[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
2931
riscv = { version = "0.14", default-features = false }
3032

31-
[package.metadata.docs.rs]
32-
rustc-args = ["--cfg", "doc"]
33-
3433
[dev-dependencies]
3534
rand = { version = "0.9.1", default-features = false, features = ["small_rng"] }
35+
36+
[package.metadata.docs.rs]
37+
all-features = true

‎page_table_multiarch/src/arch/mod.rs‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
1-
#[cfg(any(target_arch = "x86_64", doc))]
1+
#[cfg(any(target_arch = "x86_64", feature = "all"))]
22
pub mod x86_64;
33

4-
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))]
4+
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", feature = "all"))]
55
pub mod riscv;
66

7-
#[cfg(any(target_arch = "aarch64", doc))]
7+
#[cfg(any(target_arch = "aarch64", feature = "all"))]
88
pub mod aarch64;
99

10-
#[cfg(any(target_arch = "loongarch64", doc))]
10+
#[cfg(any(target_arch = "loongarch64", feature = "all"))]
1111
pub mod loongarch64;

‎page_table_multiarch/src/arch/riscv.rs‎

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -3,15 +3,6 @@
33
use crate::{PageTable64, PagingMetaData};
44
use page_table_entry::riscv::Rv64PTE;
55

6-
#[inline]
7-
fn riscv_flush_tlb(vaddr: Option<memory_addr::VirtAddr>) {
8-
if let Some(vaddr) = vaddr {
9-
riscv::asm::sfence_vma(0, vaddr.as_usize())
10-
} else {
11-
riscv::asm::sfence_vma_all();
12-
}
13-
}
14-
156
/// A virtual address that can be used in RISC-V Sv39 and Sv48 page tables.
167
pub trait SvVirtAddr: memory_addr::MemoryAddr + Send + Sync {
178
/// Flush the TLB.
@@ -21,7 +12,14 @@ pub trait SvVirtAddr: memory_addr::MemoryAddr + Send + Sync {
2112
impl SvVirtAddr for memory_addr::VirtAddr {
2213
#[inline]
2314
fn flush_tlb(vaddr: Option<Self>) {
24-
riscv_flush_tlb(vaddr.map(|vaddr| vaddr.into()))
15+
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
16+
if let Some(vaddr) = vaddr {
17+
riscv::asm::sfence_vma(0, vaddr.as_usize())
18+
} else {
19+
riscv::asm::sfence_vma_all();
20+
}
21+
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
22+
let _ = vaddr;
2523
}
2624
}
2725

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