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<title>Selected Publications</title>
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<div class="menu-category">Arda Yurdakul</div>
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<h1>Selected Publications</h1>
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<p>İ. Sıkdokur, İ. M. Baytaş and A. Yurdakul, “<a href="https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10680038">EdgeConvEns: Convolutional Ensemble Learning for Edge Intelligence,</a>” IEEE Access, DOI: 10.1109/ACCESS.2024.3460406, 2024.</p>
<p>E. Bilgili and A. Yurdakul, “<a href="https://ieeexplore.ieee.org/document/10285457">Common Subexpression-based Compression and Multiplication of Sparse Constant Matrices</a>”, IEEE Embedded Systems Letters, vol. 16, no. 2, pp. 82-85, June 2024, <a href="https://arxiv.org/pdf/2204.00057.pdf">access on arXiv</a>.</p>
<p>M. Ş. Önen and A. Yurdakul, “Container Scheduling Under ARINC 653 Scheduler Constraints,” 26th Euromicro Conference on Digital System Design (DSD’23), September 6-8, 2023, Durres, Albania.</p>
<p>C. Onur and A. Yurdakul, “<a href="https://doi.org/10.1145/3598302">ElectAnon: A Blockchain-Based, Anonymous, Robust and Scalable Ranked-Choice Voting Protocol</a>”, ACM Transactions on Distributed Ledger Technologies: Research and Practice, May 2023. <a href="https://arxiv.org/pdf/2204.00057.pdf">access on arXiv</a>.</p>
<p>C. Çağlayan and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/CaglayanDSD22.pdf">A Clustering-Based Scoring Mechanism for Malicious Model Detection in Federated Learning</a>,” 25th Euromicro Conference on Digital System Design (DSD’22), August 31 - September 2, 2022, Gran Canaria, Spain.</p>
<p>U. C. Özyar and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/OzyarITHINGS22.pdf">A Decentralized Framework with Dynamic and Event-Driven Container Orchestration at the Edge</a>,” 15th IEEE International Conference on Internet of Things (iThings’22), Aug. 22-25, 2022, Espoo Finland.</p>
<p>M. A. Şarkışla and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/SarkislaAUSPDC21.pdf">SIMDify: Framework for SIMD-Processing with RISC-V Scalar Instruction Set</a>,” 19th Australasian Symposium on Parallel and Distributed Computing (AusPDC’21), 1 - 5 February 2021, online.</p>
<p>Ö. F. Irmak and A. Yurdakul, “An Embedded RISC-V Core with Fast Modular Multiplication”, <a href="http://arxiv.org/abs/2009.14685">arXiv:2009.14685</a>, 2020.</p>
<p>İ. Sıkdokur, İ. M. Baytaş and A. Yurdakul, “<a href="https://arxiv.org/abs/2203.11081">Image Classification on Accelerated Neural Networks</a>,” 6th Turkish High Performance Computing Conference, BAŞARIM’20, Oct. 8-9, 2020, Ankara, Turkey.</p>
<p>N. Hilal and A. Yurdakul, "<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/HilalITCVT20.pdf">Model-based Design of a Roadside Unit for Emergency and
Disaster Management</a>,” 3rd International Workshop on Intelligent Transportation and Connected Vehicles Technologies (ITCVT 2020), April 20, 2020, Budapest, Hungary</p>
<p>K. R Özyılmaz and A. Yurdakul, "<a href="https://www.crcpress.com/Security-Analytics-for-the-Internet-of-Everything/Ahmed-Ullah-Pathan/p/book/9780367440923">IoT Blockchain Integration: A Security Perspective,</a>” in Security Analytics for Internet of Everything, CRC Press, Taylor & Francis Group, USA, February 2020.</p>
<p>İ. Taştan, M. Karaca and A. Yurdakul, “<a href="https://www.mdpi.com/2079-9292/9/1/125">Approximate CPU Design for IoT End-Devices with Learning Capabilities</a>,” in Special Issue Low-Power Techniques for Embedded Systems and Network-on-Chip Architectures, Electronics, vol 9., issue. 1, article no: 125, January 2020.</p>
<p>K. R. Özyılmaz and A. Yurdakul, “<a href="https://arxiv.org/abs/1809.07655">Designing a blockchain-based IoT infrastructure with Ethereum, Swarm and LoRa: The Software Solution to Create High-Availability with Security Minimal Risks,</a>” IEEE Consumer Electronics Magazine, vol. 8, pp. 28-34, March 2019.</p>
<p>K. R. Özyılmaz, M. Doğan and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/OzyilmazCVCBT18.pdf">IDMoB: IoT Data Marketplace on Blockchain,</a>” Crypto Valley Conference on Blockchain Technology (CVCBT’18), June 20-23, 2018, Zug, Switzerland.</p>
<p>A. V. Nurdağ, B. Arnrich and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/NurdagSMARTCOMP18.pdf">WiP: Daily Life Oriented Indoor Localization By Fusion Of Smartphone Sensors And Wi-Fi,</a>” 4th IEEE International Conference on Smart Computing (SMARTCOMP’18), June 18-20, 2018, Taormina, Italy.</p>
<p>M. Tükel, A. Yurdakul and B. Örs, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/TukelIVLSI18.pdf">Customizable embedded processor array for multimedia applications,</a>” Integration-The VLSI Journal, pp. 213-223, January 2018. </p>
<p>K. R. Özyılmaz and A. Yurdakul, “<a href="https://doi.org/10.1145/3125503.3125628">WiP: Integrating Low-Power IoT devices to a Blockchain-Based Infrastructure,</a>” International Conference on Embedded Software (EMSOFT’17), Oct. 15-20, 2017, Seoul, South Korea.</p>
<p>A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/FDL17.pdf">WiP: From SQL to Database Processors: A Retargetable Query Planner,</a>” Forum on Specification & Design Languages (FDL’17), Sept 18-20, 2017, Verona, Italy.</p>
<p>B. Salami, G. A. Malazgirt, O. Arcas-Abella, A. Yurdakul and N. Sönmez, “<a href="https://doi.org/10.1016/j.micpro.2017.04.018">AxleDB: A novel programmable query processing platform on FPGA,</a>" Microprocessors and Microsystems: Embedded Hardware Design, vol. 51, pp. 142-164, June 2017. </p>
<p>G. A. Malazgirt and A. Yurdakul, “Prenaut: Design space exploration for embedded symmetric multiprocessing with various on-chip architectures,” Journal of Systems Architecture: Embedded Software Design, vol. 72, pp. 3-18, January 2017. </p>
<p>M. Schmid, C. Schmitt, F. Hannig, G. A. Malazgirt, N. Sonmez, A. Yurdakul and A. Cristal, “<a href="https://www.springer.com/gp/book/9783319264066">Big Data and HPC Acceleration with Vivado HLS,</a>” in FPGAs for Software Programmers, 2016, Springer, ISBN: 978-3-319-26406-6</p>
<p>S. Bayar and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/BayarDTIS16.pdf">An Efficient Mapping Algorithm on 2-D Mesh Network-on-Chip with Reconfigurable Switches,</a>” 11th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS’16), April 12-14, 2016, İstanbul, Turkey. </p>
<p>N. Aras and A. Yurdakul, “<a href="https://doi.org/10.1016/j.apm.2015.09.061">A New Multi-objective Mathematical Model for the High-level Synthesis of Integrated Circuits,</a>” Applied Mathematical Modelling, Volume 40, Issue 3, pp. 2274-2290, 1 February 2016.</p>
<p>G. A. Malazgirt, D. Candaş and A. Yurdakul, “<a href="https://arxiv.org/abs/1601.03341">Taxim: A Toolchain for Automated and Configurable Simulation for Embedded Multiprocessor Design,</a>” 4th International Workshop on High Performance Energy Efficient Embedded Systems (HIP3ES’16), Jan 18, 2016, Prag, Czech Republic.</p>
<p>G. A. Malazgirt, A. Yurdakul and S. Niar, “Customizing VLIW Processors from Dynamically Profiled Execution Traces,” Microprocessors and Microsystems: Embedded Hardware Design, vol. 39, no. 8, pp. 656–673, November 2015.</p>
<p>S. Bayar and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/BayarTVLSI15.pdf">PFMAP: Exploitation of Particle Filters for Network-on-chip Mapping,</a>” IEEE Transactions on VLSI Design, vol. 23, no. 10, pp. 2116 - 2127, October 2015.</p>
<p>G. A. Malazgirt, B. Kıyan, D. Candaş, K. Erdayandı and A. Yurdakul, “Exploring Embedded Symmetric Multiprocessing with Various On-chip Architectures,” 13th International Conference on Embedded and Ubiquitous Computing (EUC’15), October 21-23, 2015, Porto, Portugal.</p>
<p>G. A. Malazgirt, N. Sönmez, A. Yurdakul, O. Unsal and A. Cristal, “High Level Synthesis Based Hardware Accelator Design for Processing SQL Queries,” 12th FPGA World Conference (FPGAWORLD’15), September 8-10, 2015, Stockholm-Copenhag, Sweden-Denmark.</p>
<p>G. A. Malazgirt, N. Sönmez, A. Yurdakul, O. Unsal and A. Cristal, “Accelerating Complete Decision Support Queries Through High-Level Synthesis Technology,” 23rd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA’15), February 22-25, 2015, Monterey, California, USA.</p>
<p>S. Niar, A. Yurdakul, O. Unsal, T. Tugcu and A. Yuceturk, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/NiarICCVE14.pdf">A Dynamically Reconfigurable Architecture for Emergency and Disaster Management in ITS,</a>” 3rd International Conference on Connected Vehicles and Expo (ICCVE’14), Nov 3-7, 2014, Vienna, Austria.</p>
<p>G. A. Malazgirt, H.E. Yantır, A. Yurdakul and S. Niar, “Application Specific Multi-port Memory Customization in FPGAs," 24th International Conference on Field Programmable Logic and Applications (FPL’14), September 2 - 4, 2014, Munich, Germany.</p>
<p>G. A. Malazgirt, A. Yurdakul and S. Niar, “WiP: MIPT: Rapid Exploration and Evaluation for Migrating Sequential Algorithms to Multiprocessing," 12th International Conference on High Performance Computing & Simulation (HPCS’14), July 21 - 25, 2014, Bologna, Italy.</p>
<p>H. E. Yantır and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/YantirRAW14.pdf">An Efficient Heterogeneous Register File Implementation for FPGAs,</a>" IEEE 21st Reconfigurable Architectures Workshop (RAW’14), 19-20 May 2014, Phoenix, USA.</p>
<p>H. E. Yantır, S. Bayar and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/YantirDSD13.pdf">Efficient Implementations of Multi-pumped Multi-port Register Files in FPGAs,</a>” 16th Euromicro Conference on Digital System Design (DSD’13), September 4–6, 2013, Santander, Spain.</p>
<p>D. Fennibay, A. Yurdakul and A. Şen, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/FennibayTCAD12.pdf">Introducing A Heterogeneous Simulation and Modeling Framework for Automation Systems,</a>” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 31, pp 1642-1655, November 2012.</p>
<p>G. A. Malazgirt, E. Çulha, A. Sen, İ. F. Başkaya and A. Yurdakul, "<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/MalazgirtDSD12.pdf">A Verifiable High Level Data Path Synthesis Framework,</a>” 15th Euromicro Conference on Digital System Design (DSD’12), September 5–8, 2012, Izmir, Turkey.</p>
<p>S. Bayar and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/BayarJSA12.pdf">A Dynamically Reconfigurable Communication Architecture For Multicore Embedded Systems,</a>” Journal of Systems Architecture, vol. 58, pp. 140-159, February 2012.</p>
<p>S. Bayar, M. Tükel and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/BayarRECOSOC11.pdf">A Self-Reconfigurable Platform for General Purpose Image Processing Systems on Low-Cost Spartan-6 FPGAs,</a>” 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoc’11), June 20-22, 2011, Montpellier, France.</p>
<p>A. Yurdakul, B. Kurumahmut, G Kabukcu, “<a href="https://www.springer.com/gp/book/9789048193035">Generic Model for Application-Specific Processors on Reconfigurable Fabric,</a>" in Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s, Vol. 63, August 2010.</p>
<p>D. Fennibay, A. Yurdakul and A. Şen, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/FennibayICESS10.pdf">Introducing Hardware-in-Loop Concept to the Hardware/Software Co-design of Real-time Embedded Systems,</a>” Proceedings of the 7th IEEE International Conference on Embedded Software and Systems (ICESS’10), June 29-July 1, 2010, Bradford, United Kingdom.</p>
<p>D. Fennibay, A. Yurdakul and A. Şen, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/FennibayDATE10W.pdf">Hardware-in-the-loop for hardware/software co-design of real-time embedded systems,</a>” DATE’10 Workshop: Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, March 8-12, 2010, Frankfurt, Germany.</p>
<p>R. Ghamari and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/GhamariWRC10.pdf">Register File Design in Automatically Generated ASIPs,</a>” 4th HiPEAC Workshop on Reconfigurable Computing (WRC’10), Jan 23, 2010, Pisa, Italy.</p>
<p>B. Kurumahmut, G. Kabukcu, R. Ghamari and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/KurumahmutFDL09.pdf">Design Automation Model for Application-Specific Processors on Reconfigurable Fabric,</a>” Proceedings of Forum on Specification & Design Languages (FDL’09) , Sept. 22-24, 2009, Sophia Antipolis, France.</p>
<p>M. Erkoç and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/ErkocISCIS09.pdf">Halftoning Soft Cores for Low-Cost Digital Displays,</a>” Proceedings of 24th International SympoSİUm on Computer and Information Sciences (ISCIS’09), Sept. 14-16, 2009, Northern Cyprus.</p>
<p>M. Aktan, A. Yurdakul and G. Dündar, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/AktanTCAS08.pdf">An Algorithm for the Design of Low-Power Hardware Efficient FIR Filters,</a>” IEEE Transactions on Circuits and Systems-I, vol. 55, no. 6, pp. 1536-1545, July 2008.</p>
<p>S. Bayar and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/BayarPRIME08.pdf">Self-Reconfiguration on Spartan-III FPGAs with Compressed Partial Bitstreams via a Parallel Configuration Access Port (cPCAP) Core,</a>” Proceedings of 4th conference on Ph.D. Research in Microelectronics and Electronics (PRIME’08), İstanbul, Turkey, 2008.</p>
<p>S. Bayar and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/BayarWRC08.pdf">Dynamic Partial Self-Reconfiguration on Spartan-III FPGAs via a Parallel Configuration Access Port (PCAP),</a>” Proceedings of 2nd HiPEAC Workshop on Reconfigurable Computing (WRC’08), Goteborg, Sweden, 2008.</p>
<p>G. Kabukcu and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/KabukcuJIST07.pdf">Low-Cost Solution to On-Line CFA Demosaicking,</a>” International Journal of Imaging Systems and Technology, vol. 17, no. 4, pp. 232-243, December 2007.</p>
<p>N. Sönmez and A. Yurdakul, "<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/SonmezSOC06.pdf">SIxD: A Configurable Application-Specific SISD/SIMD Soft-Core,</a>” International Symposium on System-on-Chip (SoC’06), Tampere, Finland, 2006.</p>
<p>A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/IVLSI05.pdf">Multiplierless Implementation of 2D FIR Filters,</a>” Integration-The VLSI Journal, Volume 38, Issue 4 , pp 597-613, April 2005.</p>
<p>A. Özpınar and A. Yurdakul, "<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/OzpinarDSD03.pdf">Configurable Design and Implementation of the Rijndael Algorithm-AES,</a>” 6th Euromicro Conference on Digital System Design (DSD’03), Antalya, Turkey, 2003.</p>
<p>A. Yurdakul and G. Dündar, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/IEE02.pdf">A Fast and Efficient Algorithm for the Multiplierless Realization of Linear DSP Transforms,</a>” IEE-Proceedings-Circuits Devices, and Systems, vol 149, pp 205-211, 2002.</p>
<p>A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/DSP02.pdf">An Efficient Algorithm for the Multiplierless Realization of 2-D Linear Transforms,</a>" IEEE 10th Digital Signal Processing Workshop (DSP’02), Atlanta, USA, 2002.</p>
<p>J. O. Coleman and A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/ColemanCISS01.pdf,">Fractions in the Canonical-Signed-Digit Number System,</a>” 35th Conference on Information Sciences and Systems (CISS’01), Baltimore, Maryland, USA, 2001.</p>
<p>A. Yurdakul, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/ISCAS00.pdf">A Synthesis Tool for the Multiplierless Realization of FIR-Based Multirate DSP Systems,</a>” IEEE International Symposium on Circuits and Systems (ISCAS’00), vol. 4, pp. 69-72, Geneva, Switzerland, May 28-31, 2000.</p>
<p>A. Yurdakul and G. Dündar, “<a href="http://www.cmpe.boun.edu.tr/~yurdakul/publications/JVLSI99.pdf">Multiplierless Realization of Linear DSP Transforms by Using Common Two-Term Expressions,</a>” Kluwer Journal of VLSI Signal Processing, vol. 22, pp 163-172, 1999.</p>
<p>A. Yurdakul and G. Dündar, “Statistical Methods for the Estimation of Quantization Effects in FIR-Based Multirate Systems,” IEEE Transactions on Signal Processing, vol. 47, pp 1749-1753, June 1999.</p>
<p>A. Yurdakul and G. Dündar, "A New Hybrid Algorithm for Over-the-Cells Routing,” 8th Mediterranean Electrotechnical Conference (MELECON’96), vol. 3, pp. 480-483, Bari, Italy, 1996.</p>
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