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[ARC32] add missing includes
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‎src/include/arc32/power_states.h

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/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __POWER_STATES_H__
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#define __POWER_STATES_H__
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/**
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* SoC Power mode control for Quark SE Microcontrollers.
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*
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* Available SoC states are:
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* - Low Power Sensing Standby (LPSS)
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* - Sleep
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*
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* LPSS can only be enabled from the Sensor core,
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* refer to @ref ss_power_soc_lpss_enable for further details.
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*
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* @defgroup groupSoCPower Quark SE SoC Power states
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* @{
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*/
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/**
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* Enter SoC sleep state.
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*
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* Put the SoC into sleep state until next SoC wake event.
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*
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* - Core well is turned off
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* - Always on well is on
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* - Hybrid Clock is off
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* - RTC Clock is on
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*
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* Possible SoC wake events are:
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* - Low Power Comparator Interrupt
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* - AON GPIO Interrupt
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* - AON Timer Interrupt
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* - RTC Interrupt
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*/
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void power_soc_sleep(void);
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/**
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* Enter SoC deep sleep state.
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*
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* Put the SoC into deep sleep state until next SoC wake event.
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*
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* - Core well is turned off
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* - Always on well is on
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* - Hybrid Clock is off
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* - RTC Clock is on
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*
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* Possible SoC wake events are:
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* - Low Power Comparator Interrupt
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* - AON GPIO Interrupt
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* - AON Timer Interrupt
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* - RTC Interrupt
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*
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* This function puts 1P8V regulators and 3P3V into Linear Mode.
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*/
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void power_soc_deep_sleep(void);
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/**
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* @}
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*/
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#endif /* __POWER_STATES_H__ */

‎src/include/arc32/qm_interrupt_router_regs.h

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/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __QM_INTERRUPT_ROUTER_REGS_H__
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#define __QM_INTERRUPT_ROUTER_REGS_H__
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/**
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* Quark SE SoC Event Router registers.
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*
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* @defgroup groupQUARKSESEEVENTROUTER SoC Event Router (SE)
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* @{
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*/
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/**
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* Masks for single source interrupts in the Event Router.
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* To enable: reg &= ~(MASK)
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* To disable: reg |= MASK;
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*/
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#define QM_IR_INT_LMT_MASK BIT(0)
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#define QM_IR_INT_SS_MASK BIT(8)
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/* Masks for single source halts in the Event Router. */
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#define QM_IR_INT_LMT_HALT_MASK BIT(16)
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#define QM_IR_INT_SS_HALT_MASK BIT(24)
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/* Event Router Unmask interrupts for a peripheral. */
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#define QM_IR_UNMASK_LMT_INTERRUPTS(_peripheral_) \
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(_peripheral_ &= ~(QM_IR_INT_LMT_MASK))
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#define QM_IR_UNMASK_SS_INTERRUPTS(_peripheral_) \
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(_peripheral_ &= ~(QM_IR_INT_SS_MASK))
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/* Mask interrupts for a peripheral. */
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#define QM_IR_MASK_LMT_INTERRUPTS(_peripheral_) \
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(_peripheral_ |= QM_IR_INT_LMT_MASK)
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#define QM_IR_MASK_SS_INTERRUPTS(_peripheral_) \
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(_peripheral_ |= QM_IR_INT_SS_MASK)
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/* Unmask halt for a peripheral. */
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#define QM_IR_UNMASK_LMT_HALTS(_peripheral_) \
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(_peripheral_ &= ~(QM_IR_INT_LMT_HALT_MASK))
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#define QM_IR_UNMASK_SS_HALTS(_peripheral_) \
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(_peripheral_ &= ~(QM_IR_INT_SS_HALT_MASK))
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/* Mask halt for a peripheral. */
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#define QM_IR_MASK_LMT_HALTS(_peripheral_) \
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(_peripheral_ |= QM_IR_INT_LMT_HALT_MASK)
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#define QM_IR_MASK_SS_HALTS(_peripheral_) \
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(_peripheral_ |= QM_IR_INT_SS_HALT_MASK)
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#define QM_IR_GET_LMT_MASK(_peripheral_) (_peripheral_ & QM_IR_INT_LMT_MASK)
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#define QM_IR_GET_LMT_HALT_MASK(_peripheral_) \
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(_peripheral_ & QM_IR_INT_LMT_HALT_MASK)
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#define QM_IR_GET_SS_MASK(_peripheral_) (_peripheral_ & QM_IR_INT_SS_MASK)
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#define QM_IR_GET_SS_HALT_MASK(_peripheral_) \
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(_peripheral_ & QM_IR_INT_SS_HALT_MASK)
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/* Define macros for use by the active core. */
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#if (QM_LAKEMONT)
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#define QM_IR_UNMASK_INTERRUPTS(_peripheral_) \
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QM_IR_UNMASK_LMT_INTERRUPTS(_peripheral_)
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#define QM_IR_MASK_INTERRUPTS(_peripheral_) \
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QM_IR_MASK_LMT_INTERRUPTS(_peripheral_)
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#define QM_IR_UNMASK_HALTS(_peripheral_) QM_IR_UNMASK_LMT_HALTS(_peripheral_)
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#define QM_IR_MASK_HALTS(_peripheral_) QM_IR_MASK_LMT_HALTS(_peripheral_)
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#define QM_IR_INT_MASK QM_IR_INT_LMT_MASK
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#define QM_IR_INT_HALT_MASK QM_IR_INT_LMT_HALT_MASK
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#define QM_IR_GET_MASK(_peripheral_) QM_IR_GET_LMT_MASK(_peripheral_)
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#define QM_IR_GET_HALT_MASK(_peripheral_) QM_IR_GET_LMT_HALT_MASK(_peripheral_)
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#elif(QM_SENSOR)
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#define QM_IR_UNMASK_INTERRUPTS(_peripheral_) \
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QM_IR_UNMASK_SS_INTERRUPTS(_peripheral_)
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#define QM_IR_MASK_INTERRUPTS(_peripheral_) \
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QM_IR_MASK_SS_INTERRUPTS(_peripheral_)
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#define QM_IR_UNMASK_HALTS(_peripheral_) QM_IR_UNMASK_SS_HALTS(_peripheral_)
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#define QM_IR_MASK_HALTS(_peripheral_) QM_IR_MASK_SS_HALTS(_peripheral_)
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#define QM_IR_INT_MASK QM_IR_INT_SS_MASK
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#define QM_IR_INT_HALT_MASK QM_IR_INT_SS_HALT_MASK
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#define QM_IR_GET_MASK(_peripheral_) QM_IR_GET_SS_MASK(_peripheral_)
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#define QM_IR_GET_HALT_MASK(_peripheral_) QM_IR_GET_SS_HALT_MASK(_peripheral_)
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#else
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#error "No active core selected."
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#endif
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/** SS I2C Interrupt register map. */
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typedef struct {
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QM_RW uint32_t err_mask;
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QM_RW uint32_t rx_avail_mask;
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QM_RW uint32_t tx_req_mask;
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QM_RW uint32_t stop_det_mask;
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} int_ss_i2c_reg_t;
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/** SS SPI Interrupt register map. */
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typedef struct {
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QM_RW uint32_t err_int_mask;
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QM_RW uint32_t rx_avail_mask;
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QM_RW uint32_t tx_req_mask;
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} int_ss_spi_reg_t;
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/** Interrupt register map. */
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typedef struct {
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QM_RW uint32_t ss_adc_0_error_int_mask; /**< Sensor ADC 0 Error. */
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QM_RW uint32_t ss_adc_0_int_mask; /**< Sensor ADC 0. */
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QM_RW uint32_t ss_gpio_0_int_mask; /**< Sensor GPIO 0. */
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QM_RW uint32_t ss_gpio_1_int_mask; /**< Sensor GPIO 1. */
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int_ss_i2c_reg_t ss_i2c_0_int; /**< Sensor I2C 0 Masks. */
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int_ss_i2c_reg_t ss_i2c_1_int; /**< Sensor I2C 1 Masks. */
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int_ss_spi_reg_t ss_spi_0_int; /**< Sensor SPI 0 Masks. */
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int_ss_spi_reg_t ss_spi_1_int; /**< Sensor SPI 1 Masks. */
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QM_RW uint32_t i2c_master_0_int_mask; /**< I2C Master 0. */
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QM_RW uint32_t i2c_master_1_int_mask; /**< I2C Master 1. */
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QM_R uint32_t reserved;
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QM_RW uint32_t spi_master_0_int_mask; /**< SPI Master 0. */
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QM_RW uint32_t spi_master_1_int_mask; /**< SPI Master 1. */
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QM_RW uint32_t spi_slave_0_int_mask; /**< SPI Slave 0. */
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QM_RW uint32_t uart_0_int_mask; /**< UART 0. */
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QM_RW uint32_t uart_1_int_mask; /**< UART 1. */
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QM_RW uint32_t i2s_0_int_mask; /**< I2S 0. */
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QM_RW uint32_t gpio_0_int_mask; /**< GPIO 0. */
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QM_RW uint32_t pwm_0_int_mask; /**< PWM 0. */
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QM_RW uint32_t usb_0_int_mask; /**< USB 0. */
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QM_RW uint32_t rtc_0_int_mask; /**< RTC 0. */
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QM_RW uint32_t wdt_0_int_mask; /**< WDT 0. */
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QM_RW uint32_t dma_0_int_0_mask; /**< DMA 0 Ch 0. */
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QM_RW uint32_t dma_0_int_1_mask; /**< DMA 0 Ch 1. */
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QM_RW uint32_t dma_0_int_2_mask; /**< DMA 0 Ch 2. */
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QM_RW uint32_t dma_0_int_3_mask; /**< DMA 0 Ch 3. */
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QM_RW uint32_t dma_0_int_4_mask; /**< DMA 0 Ch 4. */
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QM_RW uint32_t dma_0_int_5_mask; /**< DMA 0 Ch 5. */
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QM_RW uint32_t dma_0_int_6_mask; /**< DMA 0 Ch 6. */
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QM_RW uint32_t dma_0_int_7_mask; /**< DMA 0 Ch 7. */
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/** Mailbox 0 Combined 8 Channel Host and Sensor Masks. */
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QM_RW uint32_t mailbox_0_int_mask;
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/** Comparator Sensor Halt Mask. */
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QM_RW uint32_t comparator_0_ss_halt_int_mask;
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/** Comparator Host Halt Mask. */
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QM_RW uint32_t comparator_0_host_halt_int_mask;
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/** Comparator Sensor Mask. */
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QM_RW uint32_t comparator_0_ss_int_mask;
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/** Comparator Host Mask. */
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QM_RW uint32_t comparator_0_host_int_mask;
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QM_RW uint32_t host_bus_error_int_mask; /**< Host bus error. */
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QM_RW uint32_t dma_0_error_int_mask; /**< DMA 0 Error. */
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QM_RW uint32_t sram_mpr_0_int_mask; /**< SRAM MPR 0. */
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QM_RW uint32_t flash_mpr_0_int_mask; /**< Flash MPR 0. */
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QM_RW uint32_t flash_mpr_1_int_mask; /**< Flash MPR 1. */
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QM_RW uint32_t aonpt_0_int_mask; /**< AONPT 0. */
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QM_RW uint32_t adc_0_pwr_int_mask; /**< ADC 0 PWR. */
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QM_RW uint32_t adc_0_cal_int_mask; /**< ADC 0 CAL. */
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QM_RW uint32_t aon_gpio_0_int_mask; /**< AON GPIO 0. */
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QM_RW uint32_t lock_int_mask_reg; /**< Interrupt Mask Lock Register. */
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} qm_interrupt_router_reg_t;
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/* Number of SCSS interrupt mask registers (excluding mask lock register). */
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#define QM_INTERRUPT_ROUTER_MASK_NUMREG \
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((sizeof(qm_interrupt_router_reg_t) / sizeof(uint32_t)) - 1)
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/* Default POR SCSS interrupt mask (all interrupts masked). */
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#define QM_INTERRUPT_ROUTER_MASK_DEFAULT (0xFFFFFFFF)
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#if (UNIT_TEST)
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qm_interrupt_router_reg_t test_interrupt_router;
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#define QM_INTERRUPT_ROUTER \
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((qm_interrupt_router_reg_t *)(&test_interrupt_router))
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#else
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/* System control subsystem interrupt masking register block. */
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#define QM_INTERRUPT_ROUTER_BASE (0xB0800400)
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#define QM_INTERRUPT_ROUTER \
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((qm_interrupt_router_reg_t *)QM_INTERRUPT_ROUTER_BASE)
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#endif
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#define QM_IR_DMA_ERROR_HOST_MASK (0x000000FF)
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#define QM_IR_DMA_ERROR_SS_MASK (0x0000FF00)
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/** @} */
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#endif /* __QM_INTERRUPT_ROUTER_REGS_H__ */

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