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Opta: initial: Add target
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‎connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt

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@@ -5,6 +5,8 @@ if("DISCO_H747I" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_DISCO_H747I)
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elseif("PORTENTA_H7" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_PORTENTA_H7)
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elseif("OPTA" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_OPTA)
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elseif("NUCLEO_H743ZI" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_NUCLEO_H743ZI)
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elseif("NUCLEO_H743ZI2" IN_LIST MBED_TARGET_LABELS)

‎connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_OPTA/CMakeLists.txt

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# Copyright (c) 2020 ARM Limited. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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target_sources(mbed-emac
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INTERFACE
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stm32h7_eth_init.c
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)

‎connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_OPTA/stm32h7_eth_init.c

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/* mbed Microcontroller Library
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* Copyright (c) 2018, STMicroelectronics
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* Copyright (c) 2020, Arduino SA
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define ETHERNET 1
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#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
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#include "stm32h7xx_hal.h"
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#include "opta_power.h"
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#define ETH_TX_EN_Pin GPIO_PIN_11
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#define ETH_TX_EN_GPIO_Port GPIOG
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#define ETH_TXD1_Pin GPIO_PIN_12
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#define ETH_TXD1_GPIO_Port GPIOG
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#define ETH_TXD0_Pin GPIO_PIN_13
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#define ETH_TXD0_GPIO_Port GPIOG
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#define ETH_MDC_SAI4_D1_Pin GPIO_PIN_1
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#define ETH_MDC_SAI4_D1_GPIO_Port GPIOC
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#define ETH_MDIO_Pin GPIO_PIN_2
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#define ETH_MDIO_GPIO_Port GPIOA
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#define ETH_REF_CLK_Pin GPIO_PIN_1
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#define ETH_REF_CLK_GPIO_Port GPIOA
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#define ETH_CRS_DV_Pin GPIO_PIN_7
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#define ETH_CRS_DV_GPIO_Port GPIOA
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#define ETH_RXD0_Pin GPIO_PIN_4
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#define ETH_RXD0_GPIO_Port GPIOC
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#define ETH_RXD1_Pin GPIO_PIN_5
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#define ETH_RXD1_GPIO_Port GPIOC
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/**
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* Override HAL Eth Init function
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*/
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void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
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{
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GPIO_InitTypeDef GPIO_InitStruct;
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if (heth->Instance == ETH) {
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enableEthPowerSupply();
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#if !(defined(DUAL_CORE) && defined(CORE_CM4))
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/* Disable DCache for STM32H7 family */
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SCB_DisableDCache();
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#endif
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/* GPIO Ports Clock Enable */
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__HAL_RCC_GPIOA_CLK_ENABLE();
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// __HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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// __HAL_RCC_GPIOH_CLK_ENABLE();
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/* Enable Peripheral clock */
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__HAL_RCC_ETH1MAC_CLK_ENABLE();
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__HAL_RCC_ETH1TX_CLK_ENABLE();
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__HAL_RCC_ETH1RX_CLK_ENABLE();
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/* Set pinstrap for 100mbit */
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// TODO
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/* Reset ETH Phy */
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__HAL_RCC_GPIOJ_CLK_ENABLE();
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GPIO_InitTypeDef gpio_eth_rst_init_structure;
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gpio_eth_rst_init_structure.Pin = GPIO_PIN_15;
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gpio_eth_rst_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
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gpio_eth_rst_init_structure.Pull = GPIO_NOPULL;
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gpio_eth_rst_init_structure.Speed = GPIO_SPEED_FREQ_LOW;
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HAL_GPIO_Init(GPIOJ, &gpio_eth_rst_init_structure);
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gpio_eth_rst_init_structure.Pin = ETH_RXD0_Pin | ETH_RXD1_Pin;
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HAL_GPIO_Init(GPIOC, &gpio_eth_rst_init_structure);
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HAL_GPIO_WritePin(GPIOC, ETH_RXD0_Pin, 1);
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HAL_GPIO_WritePin(GPIOC, ETH_RXD1_Pin, 1);
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gpio_eth_rst_init_structure.Pin = ETH_CRS_DV_Pin;
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HAL_GPIO_Init(GPIOA, &gpio_eth_rst_init_structure);
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HAL_GPIO_WritePin(GPIOA, ETH_CRS_DV_Pin, 1);
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HAL_Delay(25);
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HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0);
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HAL_Delay(100);
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HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 1);
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/**ETH GPIO Configuration
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PG11 ------> ETH_TX_EN
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PG12 ------> ETH_TXD1
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PG13 ------> ETH_TXD0
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PC1 ------> ETH_MDC
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PA2 ------> ETH_MDIO
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PA1 ------> ETH_REF_CLK
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PA7 ------> ETH_CRS_DV
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PC4 ------> ETH_RXD0
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PC5 ------> ETH_RXD1
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*/
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GPIO_InitStruct.Pin = ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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}
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}
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/**
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* Override HAL Eth DeInit function
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*/
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void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
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{
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if (heth->Instance == ETH) {
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/* Peripheral clock disable */
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__HAL_RCC_ETH1MAC_CLK_DISABLE();
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__HAL_RCC_ETH1TX_CLK_DISABLE();
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__HAL_RCC_ETH1RX_CLK_DISABLE();
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/**ETH GPIO Configuration
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PG11 ------> ETH_TX_EN
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PG12 ------> ETH_TXD1
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PG13 ------> ETH_TXD0
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PC1 ------> ETH_MDC
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PA2 ------> ETH_MDIO
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PA1 ------> ETH_REF_CLK
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PA7 ------> ETH_CRS_DV
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PC4 ------> ETH_RXD0
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PC5 ------> ETH_RXD1
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*/
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HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin);
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HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin);
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HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin);
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HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0);
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}
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}
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#endif /* USE_USER_DEFINED_HAL_ETH_MSPINIT */

‎connectivity/lwipstack/mbed_lib.json

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"NICLA_VISION": {
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"mem-size": 16000
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},
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"OPTA": {
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"mem-size": 16000
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},
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"FVP_MPS2_M3": {
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"mem-size": 36560
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},

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/CMakeLists.txt

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# Copyright (c) 2020 ARM Limited. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(COMPONENT_WHD EXCLUDE_FROM_ALL)
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add_library(mbed-opta INTERFACE)
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target_sources(mbed-opta
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INTERFACE
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PeripheralPins.c
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system_clock_override.c
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opta_power.cpp
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)
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target_include_directories(mbed-opta
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INTERFACE
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.
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)
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target_link_libraries(mbed-opta INTERFACE mbed-stm32h747xi-cm7)

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/CMakeLists.txt

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# Copyright (c) 2020 ARM Limited. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(firmware)

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/firmware/CMakeLists.txt

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# Copyright (c) 2020 ARM Limited. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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if("4343W_FS" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(COMPONENT_4343W)
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endif()

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt

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# Copyright (c) 2020 ARM Limited. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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target_sources(mbed-ble
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INTERFACE
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w_bt_firmware_controller.c
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)

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