@@ -210,17 +210,6 @@ TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr)
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return & xfer_status [epnum ][dir ];
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}
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- // Using a function due to better type checks
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- // This seems better than having to do type casts everywhere else
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- TU_ATTR_ALWAYS_INLINE static inline void reg16_clear_bits (__IO uint16_t * reg , uint16_t mask ) {
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- * reg = (uint16_t )(* reg & ~mask );
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- }
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-
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- // Bits in ISTR are cleared upon writing 0
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- TU_ATTR_ALWAYS_INLINE static inline void clear_istr_bits (uint32_t mask ) {
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- USB -> ISTR = ~mask ;
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- }
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-
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//--------------------------------------------------------------------+
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// Controller API
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//--------------------------------------------------------------------+
@@ -244,11 +233,7 @@ void dcd_init (uint8_t rhport)
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asm("NOP" );
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}
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- #ifdef PMA_32BIT_ACCESS // CNTR register is 32bits on STM32G0, 16bit on older versions
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USB -> CNTR &= ~USB_CNTR_PDWN ;
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- #else
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- reg16_clear_bits (& USB -> CNTR , USB_CNTR_PDWN );// Remove powerdown
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- #endif
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// Wait startup time, for F042 and F070, this is <= 1 us.
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for (uint32_t i = 0 ; i < 200 ; i ++ ) // should be a few us
@@ -492,7 +477,6 @@ static void dcd_handle_bus_reset(void)
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//__IO uint16_t * const epreg = &(EPREG(0));
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USB -> DADDR = 0u ; // disable USB peripheral by clearing the EF flag
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-
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for (uint32_t i = 0 ; i < STFSDEV_EP_COUNT ; i ++ )
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{
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// Clear all EPREG (or maybe this is automatic? I'm not sure)
@@ -683,13 +667,13 @@ void dcd_int_handler(uint8_t rhport) {
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/* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */
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if (int_status & USB_ISTR_SOF ) {
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- clear_istr_bits ( USB_ISTR_SOF ) ;
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+ USB -> ISTR &=~ USB_ISTR_SOF ;
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dcd_event_sof (0 , USB -> FNR & USB_FNR_FN , true);
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}
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if (int_status & USB_ISTR_RESET ) {
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// USBRST is start of reset.
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- clear_istr_bits ( USB_ISTR_RESET ) ;
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+ USB -> ISTR &=~ USB_ISTR_RESET ;
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dcd_handle_bus_reset ();
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dcd_event_bus_reset (0 , TUSB_SPEED_FULL , true);
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return ; // Don't do the rest of the things here; perhaps they've been cleared?
@@ -704,14 +688,10 @@ void dcd_int_handler(uint8_t rhport) {
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if (int_status & USB_ISTR_WKUP )
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{
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- #ifdef PMA_32BIT_ACCESS // CNTR register is 32bits on STM32G0, 16bit on older versions
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USB -> CNTR &= ~USB_CNTR_LPMODE ;
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USB -> CNTR &= ~USB_CNTR_FSUSP ;
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- #else
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- reg16_clear_bits (& USB -> CNTR , USB_CNTR_LPMODE );
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- reg16_clear_bits (& USB -> CNTR , USB_CNTR_FSUSP );
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- #endif
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- clear_istr_bits (USB_ISTR_WKUP );
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+
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+ USB -> ISTR &=~USB_ISTR_WKUP ;
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dcd_event_bus_signal (0 , DCD_EVENT_RESUME , true);
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}
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@@ -725,7 +705,7 @@ void dcd_int_handler(uint8_t rhport) {
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USB -> CNTR |= USB_CNTR_LPMODE ;
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/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
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- clear_istr_bits ( USB_ISTR_SUSP ) ;
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+ USB -> ISTR &=~ USB_ISTR_SUSP ;
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dcd_event_bus_signal (0 , DCD_EVENT_SUSPEND , true);
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}
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@@ -738,7 +718,7 @@ void dcd_int_handler(uint8_t rhport) {
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{
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remoteWakeCountdown -- ;
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}
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- clear_istr_bits ( USB_ISTR_ESOF ) ;
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+ USB -> ISTR &=~ USB_ISTR_ESOF ;
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}
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}
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@@ -759,13 +739,8 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
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uint8_t const dev_addr = (uint8_t ) request -> wValue ;
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// Setting new address after the whole request is complete
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- #ifdef PMA_32BIT_ACCESS
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USB -> DADDR &= ~USB_DADDR_ADD ;
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- USB -> DADDR = (USB -> DADDR & ~USB_DADDR_ADD_Msk ) | dev_addr ; // leave the enable bit set
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- #else
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- reg16_clear_bits (& USB -> DADDR , USB_DADDR_ADD );
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- USB -> DADDR = (uint16_t )(USB -> DADDR | dev_addr ); // leave the enable bit set
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- #endif
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+ USB -> DADDR |= dev_addr ; // leave the enable bit set
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}
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}
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