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hathachhathach
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dma rx works well
1 parent fc76195 commit 9c2a849

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+267
-14
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3 files changed

+267
-14
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‎hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc

Lines changed: 194 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,194 @@
1+
#MicroXplorer Configuration settings - do not modify
2+
CAD.formats=
3+
CAD.pinconfig=
4+
CAD.provider=
5+
Dma.Request0=UCPD1_RX
6+
Dma.Request1=UCPD1_TX
7+
Dma.RequestsNb=2
8+
Dma.UCPD1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
9+
Dma.UCPD1_RX.0.EventEnable=DISABLE
10+
Dma.UCPD1_RX.0.Instance=DMA1_Channel1
11+
Dma.UCPD1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
12+
Dma.UCPD1_RX.0.MemInc=DMA_MINC_ENABLE
13+
Dma.UCPD1_RX.0.Mode=DMA_NORMAL
14+
Dma.UCPD1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
15+
Dma.UCPD1_RX.0.PeriphInc=DMA_PINC_DISABLE
16+
Dma.UCPD1_RX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
17+
Dma.UCPD1_RX.0.Priority=DMA_PRIORITY_HIGH
18+
Dma.UCPD1_RX.0.RequestNumber=1
19+
Dma.UCPD1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
20+
Dma.UCPD1_RX.0.SignalID=NONE
21+
Dma.UCPD1_RX.0.SyncEnable=DISABLE
22+
Dma.UCPD1_RX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
23+
Dma.UCPD1_RX.0.SyncRequestNumber=1
24+
Dma.UCPD1_RX.0.SyncSignalID=NONE
25+
Dma.UCPD1_TX.1.Direction=DMA_MEMORY_TO_PERIPH
26+
Dma.UCPD1_TX.1.EventEnable=DISABLE
27+
Dma.UCPD1_TX.1.Instance=DMA1_Channel2
28+
Dma.UCPD1_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
29+
Dma.UCPD1_TX.1.MemInc=DMA_MINC_ENABLE
30+
Dma.UCPD1_TX.1.Mode=DMA_NORMAL
31+
Dma.UCPD1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
32+
Dma.UCPD1_TX.1.PeriphInc=DMA_PINC_DISABLE
33+
Dma.UCPD1_TX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
34+
Dma.UCPD1_TX.1.Priority=DMA_PRIORITY_HIGH
35+
Dma.UCPD1_TX.1.RequestNumber=1
36+
Dma.UCPD1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
37+
Dma.UCPD1_TX.1.SignalID=NONE
38+
Dma.UCPD1_TX.1.SyncEnable=DISABLE
39+
Dma.UCPD1_TX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
40+
Dma.UCPD1_TX.1.SyncRequestNumber=1
41+
Dma.UCPD1_TX.1.SyncSignalID=NONE
42+
File.Version=6
43+
GPIO.groupedBy=Group By Peripherals
44+
KeepUserPlacement=true
45+
Mcu.CPN=STM32G474RET3
46+
Mcu.Family=STM32G4
47+
Mcu.IP0=DMA
48+
Mcu.IP1=NVIC
49+
Mcu.IP2=RCC
50+
Mcu.IP3=SYS
51+
Mcu.IP4=UCPD1
52+
Mcu.IP5=USART3
53+
Mcu.IPNb=6
54+
Mcu.Name=STM32G474R(B-C-E)Tx
55+
Mcu.Package=LQFP64
56+
Mcu.Pin0=PC10
57+
Mcu.Pin1=PC11
58+
Mcu.Pin2=PB4
59+
Mcu.Pin3=PB6
60+
Mcu.Pin4=VP_SYS_VS_Systick
61+
Mcu.Pin5=VP_SYS_VS_DBSignals
62+
Mcu.PinsNb=6
63+
Mcu.ThirdPartyNb=0
64+
Mcu.UserConstants=
65+
Mcu.UserName=STM32G474RETx
66+
MxCube.Version=6.8.1
67+
MxDb.Version=DB.6.0.81
68+
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
69+
NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
70+
NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
71+
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
72+
NVIC.ForceEnableDMAVector=true
73+
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
74+
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
75+
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
76+
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
77+
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
78+
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
79+
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:false
80+
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
81+
PB4.Mode=Sink_AllSignals
82+
PB4.Signal=UCPD1_CC2
83+
PB6.Mode=Sink_AllSignals
84+
PB6.Signal=UCPD1_CC1
85+
PC10.GPIOParameters=GPIO_PuPd
86+
PC10.GPIO_PuPd=GPIO_PULLUP
87+
PC10.Mode=Asynchronous
88+
PC10.Signal=USART3_TX
89+
PC11.GPIOParameters=GPIO_PuPd
90+
PC11.GPIO_PuPd=GPIO_PULLUP
91+
PC11.Mode=Asynchronous
92+
PC11.Signal=USART3_RX
93+
PinOutPanel.RotationAngle=0
94+
ProjectManager.AskForMigrate=true
95+
ProjectManager.BackupPrevious=false
96+
ProjectManager.CompilerOptimize=6
97+
ProjectManager.ComputerToolchain=false
98+
ProjectManager.CoupleFile=false
99+
ProjectManager.CustomerFirmwarePackage=
100+
ProjectManager.DefaultFWLocation=true
101+
ProjectManager.DeletePrevious=true
102+
ProjectManager.DeviceId=STM32G474RETx
103+
ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.5.1
104+
ProjectManager.FreePins=false
105+
ProjectManager.HalAssertFull=false
106+
ProjectManager.HeapSize=0x200
107+
ProjectManager.KeepUserCode=true
108+
ProjectManager.LastFirmware=true
109+
ProjectManager.LibraryCopy=2
110+
ProjectManager.MainLocation=Src
111+
ProjectManager.NoMain=false
112+
ProjectManager.PreviousToolchain=
113+
ProjectManager.ProjectBuild=false
114+
ProjectManager.ProjectFileName=board.ioc
115+
ProjectManager.ProjectName=board
116+
ProjectManager.ProjectStructure=
117+
ProjectManager.RegisterCallBack=
118+
ProjectManager.StackSize=0x400
119+
ProjectManager.TargetToolchain=Makefile
120+
ProjectManager.ToolChainLocation=
121+
ProjectManager.UnderRoot=false
122+
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_UCPD1_Init-UCPD1-false-LL-true
123+
RCC.ADC12Freq_Value=150000000
124+
RCC.ADC345Freq_Value=150000000
125+
RCC.AHBFreq_Value=150000000
126+
RCC.APB1Freq_Value=150000000
127+
RCC.APB1TimFreq_Value=150000000
128+
RCC.APB2Freq_Value=150000000
129+
RCC.APB2TimFreq_Value=150000000
130+
RCC.CRSFreq_Value=48000000
131+
RCC.CortexFreq_Value=150000000
132+
RCC.EXTERNAL_CLOCK_VALUE=12288000
133+
RCC.FCLKCortexFreq_Value=150000000
134+
RCC.FDCANFreq_Value=150000000
135+
RCC.FamilyName=M
136+
RCC.HCLKFreq_Value=150000000
137+
RCC.HRTIM1Freq_Value=150000000
138+
RCC.HSE_VALUE=24000000
139+
RCC.HSI48_VALUE=48000000
140+
RCC.HSI_VALUE=16000000
141+
RCC.I2C1Freq_Value=150000000
142+
RCC.I2C2Freq_Value=150000000
143+
RCC.I2C3Freq_Value=150000000
144+
RCC.I2C4Freq_Value=150000000
145+
RCC.I2SFreq_Value=150000000
146+
RCC.IPParameters=ADC12Freq_Value,ADC345Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HRTIM1Freq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQ,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,QSPIFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
147+
RCC.LPTIM1Freq_Value=150000000
148+
RCC.LPUART1Freq_Value=150000000
149+
RCC.LSCOPinFreq_Value=32000
150+
RCC.LSE_VALUE=32768
151+
RCC.LSI_VALUE=32000
152+
RCC.MCO1PinFreq_Value=16000000
153+
RCC.PLLM=RCC_PLLM_DIV4
154+
RCC.PLLN=75
155+
RCC.PLLPoutputFreq_Value=150000000
156+
RCC.PLLQ=RCC_PLLQ_DIV4
157+
RCC.PLLQoutputFreq_Value=75000000
158+
RCC.PLLRCLKFreq_Value=150000000
159+
RCC.PWRFreq_Value=150000000
160+
RCC.QSPIFreq_Value=150000000
161+
RCC.RNGFreq_Value=75000000
162+
RCC.SAI1Freq_Value=150000000
163+
RCC.SYSCLKFreq_VALUE=150000000
164+
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
165+
RCC.UART4Freq_Value=150000000
166+
RCC.UART5Freq_Value=150000000
167+
RCC.USART1Freq_Value=150000000
168+
RCC.USART2Freq_Value=150000000
169+
RCC.USART3Freq_Value=150000000
170+
RCC.USBFreq_Value=75000000
171+
RCC.VCOInputFreq_Value=4000000
172+
RCC.VCOOutputFreq_Value=300000000
173+
USART3.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
174+
USART3.BaudRate=115200
175+
USART3.DMADisableonRxErrorParam=ADVFEATURE_DMA_ENABLEONRXERROR
176+
USART3.DataInvertParam=ADVFEATURE_DATAINV_DISABLE
177+
USART3.IPParameters=BaudRate,WordLength,Parity,StopBits,Mode,OverSampling,OneBitSampling,AutoBaudRateEnableParam,TxPinLevelInvertParam,RxPinLevelInvertParam,DataInvertParam,SwapParam,OverrunDisableParam,DMADisableonRxErrorParam,MSBFirstParam,VirtualMode-Asynchronous
178+
USART3.MSBFirstParam=ADVFEATURE_MSBFIRST_DISABLE
179+
USART3.Mode=MODE_TX_RX
180+
USART3.OneBitSampling=UART_ONE_BIT_SAMPLE_DISABLE
181+
USART3.OverSampling=UART_OVERSAMPLING_16
182+
USART3.OverrunDisableParam=ADVFEATURE_OVERRUN_ENABLE
183+
USART3.Parity=PARITY_ODD
184+
USART3.RxPinLevelInvertParam=ADVFEATURE_RXINV_DISABLE
185+
USART3.StopBits=STOPBITS_1
186+
USART3.SwapParam=ADVFEATURE_SWAP_DISABLE
187+
USART3.TxPinLevelInvertParam=ADVFEATURE_TXINV_DISABLE
188+
USART3.VirtualMode-Asynchronous=VM_ASYNC
189+
USART3.WordLength=WORDLENGTH_8B
190+
VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals
191+
VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals
192+
VP_SYS_VS_Systick.Mode=SysTick
193+
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
194+
board=custom

‎hw/bsp/stm32g4/family.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -144,15 +144,16 @@ void board_init(void)
144144

145145
#if 1
146146
// USB PD
147+
// Default CC1/CC2 is PB4/PB6
147148
/* PWR register access (for disabling dead battery feature) */
148149
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
149150
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC);
150151

151152
__HAL_RCC_UCPD1_CLK_ENABLE();
152153

153-
// Default CC1/CC2 is PB4/PB6
154-
// PB4 ------> UCPD1_CC2
155-
// PB6 ------> UCPD1_CC1
154+
// Enable DMA clock
155+
__HAL_RCC_DMAMUX1_CLK_ENABLE();
156+
__HAL_RCC_DMA1_CLK_ENABLE();
156157
#endif
157158

158159
}

‎src/portable/st/typec/typec_stm32.c

Lines changed: 69 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@
3131

3232
#if CFG_TUSB_MCU == OPT_MCU_STM32G4
3333
#include "stm32g4xx.h"
34+
#include "stm32g4xx_hal_dma.h"
3435
#else
3536
#error "Unsupported STM32 family"
3637
#endif
@@ -61,13 +62,46 @@ static uint32_t rx_count = 0;
6162
static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4);
6263
static uint32_t tx_count;
6364

65+
#define CFG_TUC_STM32_DMA_RX { DMA1_Channel1 }
66+
//#define CFG_TUC_STM32_DMA_TX { DMA1_Channel2 }
67+
68+
#ifdef CFG_TUC_STM32_DMA_RX
69+
static DMA_Channel_TypeDef* dma_rx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_RX;
70+
71+
TU_ATTR_ALWAYS_INLINE static inline
72+
void dma_rx_start(uint8_t rhport)
73+
{
74+
DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport];
75+
76+
dma_rx_ch->CMAR = (uint32_t) rx_buf;
77+
dma_rx_ch->CNDTR = sizeof(rx_buf);
78+
dma_rx_ch->CCR |= DMA_CCR_EN;
79+
}
80+
#endif
81+
82+
#ifdef CFG_TUC_STM32_DMA_TX
83+
static DMA_Channel_TypeDef* dma_tx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_TX;
84+
#endif
85+
6486
//--------------------------------------------------------------------+
6587
//
6688
//--------------------------------------------------------------------+
89+
#include "stm32g4xx_ll_dma.h"
6790

6891
bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
6992
(void) rhport;
7093

94+
#ifdef CFG_TUC_STM32_DMA_RX
95+
// Init DMA
96+
DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport];
97+
98+
// Peripheral -> Memory, Memory inc, 8-bit, High priority
99+
dma_rx_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1;
100+
dma_rx_ch->CPAR = (uint32_t) &UCPD1->RXDR;
101+
102+
LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_UCPD1_RX);
103+
#endif
104+
71105
// Initialization phase: CFG1
72106
UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) |
73107
(0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) |
@@ -77,7 +111,7 @@ bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
77111
// General programming sequence (with UCPD configured then enabled)
78112
if (port_type == TUSB_TYPEC_PORT_SNK) {
79113
// Enable both CC Phy
80-
UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos);
114+
UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1;
81115

82116
// Read Voltage State on CC1 & CC2 fore initial state
83117
uint32_t vstate_cc[2];
@@ -135,30 +169,48 @@ void tcd_int_handler(uint8_t rhport) {
135169
TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]);
136170

137171
uint32_t cr = UCPD1->CR;
172+
uint32_t cfg1 = UCPD1->CFG1;
138173

139174
// TODO only support SNK for now, required highest voltage for now
175+
// Enable PHY on correct CC and disable Rd on other CC
140176
if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) {
141177
TU_LOG1("Attach CC1\n");
142-
cr &= ~UCPD_CR_PHYCCSEL;
143-
cr |= UCPD_CR_PHYRXEN;
178+
179+
cr &= ~(UCPD_CR_PHYCCSEL | UCPD_CR_CCENABLE);
180+
cr |= UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_0;
144181
} else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) {
145182
TU_LOG1("Attach CC2\n");
146-
cr |= UCPD_CR_PHYCCSEL;
147-
cr |= UCPD_CR_PHYRXEN;
183+
cr &= ~UCPD_CR_CCENABLE;
184+
cr |= (UCPD_CR_PHYCCSEL | UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_1);
148185
} else {
149186
TU_LOG1("Detach\n");
150187
cr &= ~UCPD_CR_PHYRXEN;
188+
cr |= UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1;
151189
}
152190

153191
if (cr & UCPD_CR_PHYRXEN) {
154192
// Enable Interrupt
155-
UCPD1->IMR |= UCPD_IMR_TXISIE | UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
156-
UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE |
157-
UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE;
193+
uint32_t imr = UCPD1->IMR;
194+
imr |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
195+
UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | UCPD_IMR_RXORDDETIE |
196+
UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | UCPD_IMR_FRSEVTIE;
197+
198+
#ifdef CFG_TUC_STM32_DMA_RX
199+
cfg1 |= UCPD_CFG1_RXDMAEN;
200+
dma_rx_start(rhport);
201+
#else
202+
imr |= UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE;
203+
#endif
204+
205+
#ifndef CFG_TUC_STM32_DMA_TX
206+
imr |= UCPD_IMR_TXISIE;
207+
#endif
208+
209+
UCPD1->IMR = imr;
158210
}
159211

160-
// Enable PD RX
161212
UCPD1->CR = cr;
213+
UCPD1->CFG1 = cfg1;
162214

163215
// ack
164216
UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
@@ -176,6 +228,7 @@ void tcd_int_handler(uint8_t rhport) {
176228
UCPD1->ICR = UCPD_ICR_RXORDDETCF;
177229
}
178230

231+
#ifndef CFG_TUC_STM32_DMA_RX
179232
if (sr & UCPD_SR_RXNE) {
180233
// TODO DMA later
181234
do {
@@ -184,8 +237,9 @@ void tcd_int_handler(uint8_t rhport) {
184237

185238
// no ack needed
186239
}
240+
#endif
187241

188-
// End of message
242+
// Received full message
189243
if (sr & UCPD_SR_RXMSGEND) {
190244

191245
// Skip if CRC failed
@@ -213,13 +267,17 @@ void tcd_int_handler(uint8_t rhport) {
213267
// notify stack after good crc ?
214268
}
215269

270+
#ifdef CFG_TUC_STM32_DMA_RX
271+
// prepare next receive
272+
dma_rx_start(rhport);
273+
#endif
274+
216275
// ack
217276
UCPD1->ICR = UCPD_ICR_RXMSGENDCF;
218277
}
219278

220279
if (sr & UCPD_SR_RXOVR) {
221280
TU_LOG1("RXOVR\n");
222-
TU_LOG1_HEX(rx_count);
223281
// ack
224282
UCPD1->ICR = UCPD_ICR_RXOVRCF;
225283
}

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