revert board flash latency to 8

hathach · hathach · commit e02eee747774 · 2023-06-07T00:14:22.000+07:00
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
@@ -87,7 +87,7 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);
 
   //------------- HSI48 and CRS for USB -------------//
   RCC_OscInitTypeDef osc_hsi48 = {0};
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
@@ -62,8 +62,7 @@ void usbpd_init(uint8_t port_num, tusb_typec_port_type_t port_type) {
   }
 
   // Enable interrupt
-  //NVIC_SetPriority(UCPD1_IRQn, 0);
-//  NVIC_EnableIRQ(UCPD1_IRQn);
+  NVIC_EnableIRQ(UCPD1_IRQn);
 }
 
 uint8_t pd_rx_buf[262];
@@ -253,7 +252,7 @@ void board_init(void)
 
   board_vbus_sense_init();
 
-#if 0
+#if 1
   // USB PD
   /* PWR register access (for disabling dead battery feature) */
   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);

Original file line number	Diff line number	Diff line change
`@@ -62,8 +62,7 @@ void usbpd_init(uint8_t port_num, tusb_typec_port_type_t port_type) {`
`62`	`62`	`}`
`63`	`63`
`64`	`64`	`// Enable interrupt`
`65`		`- //NVIC_SetPriority(UCPD1_IRQn, 0);`
`66`		`-// NVIC_EnableIRQ(UCPD1_IRQn);`
	`65`	`+ NVIC_EnableIRQ(UCPD1_IRQn);`
`67`	`66`	`}`
`68`	`67`
`69`	`68`	`uint8_t pd_rx_buf[262];`
`@@ -253,7 +252,7 @@ void board_init(void)`
`253`	`252`
`254`	`253`	`board_vbus_sense_init();`
`255`	`254`
`256`		`-#if 0`
	`255`	`+#if 1`
`257`	`256`	`// USB PD`
`258`	`257`	`/* PWR register access (for disabling dead battery feature) */`
`259`	`258`	`LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);`