@@ -79,6 +79,9 @@ typedef struct
79
79
80
80
} xfer_td_t ;
81
81
82
+ static osal_mutex_def_t dcd_mutex_def ;
83
+ static osal_mutex_t dcd_mutex ;
84
+
82
85
// Data for managing dcd
83
86
static struct
84
87
{
@@ -154,6 +157,7 @@ static void edpt_dma_start(volatile uint32_t* reg_startep)
154
157
// Should be safe to blocking wait until previous DMA transfer complete
155
158
uint8_t const rhport = 0 ;
156
159
bool started = false;
160
+ osal_mutex_lock (dcd_mutex , OSAL_TIMEOUT_WAIT_FOREVER );
157
161
while (!started )
158
162
{
159
163
// LDREX/STREX may be needed in form of std atomic (required C11) or
@@ -170,6 +174,7 @@ static void edpt_dma_start(volatile uint32_t* reg_startep)
170
174
171
175
// osal_yield();
172
176
}
177
+ osal_mutex_unlock (dcd_mutex );
173
178
}
174
179
}
175
180
@@ -243,6 +248,7 @@ static void xact_in_dma(uint8_t epnum)
243
248
void dcd_init (uint8_t rhport )
244
249
{
245
250
TU_LOG1 ("dcd init\r\n" );
251
+ dcd_mutex = osal_mutex_create (& dcd_mutex_def );
246
252
(void ) rhport ;
247
253
}
248
254
@@ -457,11 +463,17 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
457
463
458
464
xfer_td_t * xfer = get_td (epnum , dir );
459
465
460
- dcd_int_disable (rhport );
466
+ if (!is_in_isr ()) {
467
+ osal_mutex_lock (dcd_mutex , OSAL_TIMEOUT_WAIT_FOREVER );
468
+ dcd_int_disable (rhport );
469
+ }
461
470
xfer -> buffer = buffer ;
462
471
xfer -> total_len = total_bytes ;
463
472
xfer -> actual_len = 0 ;
464
- dcd_int_enable (rhport );
473
+ if (!is_in_isr ()) {
474
+ dcd_int_enable (rhport );
475
+ osal_mutex_unlock (dcd_mutex );
476
+ }
465
477
466
478
// Control endpoint with zero-length packet and opposite direction to 1st request byte --> status stage
467
479
bool const control_status = (epnum == 0 && total_bytes == 0 && dir != tu_edpt_dir (NRF_USBD -> BMREQUESTTYPE ));
0 commit comments