@@ -307,8 +307,8 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
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regs -> status = (EHCI_INT_MASK_ALL & ~EHCI_INT_MASK_PORT_CHANGE );
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// Enable interrupts
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- regs -> inten = EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE | EHCI_INT_MASK_ASYNC_ADVANCE |
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- EHCI_INT_MASK_NXP_PERIODIC | EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_FRAMELIST_ROLLOVER ;
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+ regs -> inten = EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE |
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+ EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_FRAMELIST_ROLLOVER ;
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//------------- Asynchronous List -------------//
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ehci_qhd_t * const async_head = list_get_async_head (rhport );
@@ -768,28 +768,20 @@ void hcd_int_handler(uint8_t rhport)
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regs -> status = EHCI_INT_MASK_PORT_CHANGE ; // Acknowledge
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}
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+ // A USB transfer is completed with error
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if (int_status & EHCI_INT_MASK_ERROR ) {
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xfer_error_isr (rhport );
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regs -> status = EHCI_INT_MASK_ERROR ; // Acknowledge
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}
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- //------------- some QTD/SITD/ITD with IOC set is completed -------------//
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- if (int_status & EHCI_INT_MASK_NXP_ASYNC ) {
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- async_list_xfer_complete_isr (list_get_async_head (rhport ));
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- regs -> status = EHCI_INT_MASK_NXP_ASYNC ; // Acknowledge
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- }
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-
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- if (int_status & EHCI_INT_MASK_NXP_PERIODIC )
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- {
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- for (uint32_t i = 1 ; i <= FRAMELIST_SIZE ; i *= 2 )
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- {
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+ // A USB transfer is completed
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+ if (int_status & EHCI_INT_MASK_USB ) {
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+ for ( uint32_t i = 1 ; i <= FRAMELIST_SIZE ; i *= 2 ) {
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period_list_xfer_complete_isr (rhport , i );
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}
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- regs -> status = EHCI_INT_MASK_NXP_PERIODIC ; // Acknowledge
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- }
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- if ( int_status & EHCI_INT_MASK_USB ) {
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- // TODO standard EHCI xfer complete
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+ async_list_xfer_complete_isr ( list_get_async_head ( rhport ));
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+
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regs -> status = EHCI_INT_MASK_USB ; // Acknowledge
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}
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