Tasmota on ESP32-P4 with MIPI-DSI: performance notes + sdkconfig/LVGL tips

[TheHexaMaster]

Last few days I’ve been playing with a few ESP32-P4 dev boards (mostly Guiton display boards with MIPI-DSI panels), and I’d like to share a couple of observations for people trying to squeeze out maximum performance. If you found something interesting as well, feel free to share your findings.

Default IDF builds for ESP32-P4 in Tasmota

Because Tasmota support for ESP32-P4 is still evolving (and some features may not be fully enabled/integrated yet, such as DMA2D or L2-cache-related tuning), I ended up using a small set of custom sdkconfig options when building P4 binaries:

custom_sdkconfig  = CONFIG_COMPILER_OPTIMIZATION_PERF=y
                      CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y
                      CONFIG_GDMA_ISR_IRAM_SAFE=y 
                      CONFIG_LCD_DSI_ISR_IRAM_SAFE=y
                      CONFIG_LCD_DSI_ISR_CACHE_SAFE=y
                      CONFIG_SPIRAM_XIP_FROM_PSRAM=y
                      CONFIG_ESPTOOLPY_FLASHMODE="qio"
                      CONFIG_TOUCH_CTRL_FUNC_IN_IRAM=y
                      CONFIG_TOUCH_ISR_IRAM_SAFE=y
                      CONFIG_I2C_ISR_IRAM_SAFE=y
                      CONFIG_CACHE_L2_CACHE_128KB=y
                      CONFIG_CACHE_L2_CACHE_SIZE=0x20000 
                      '# CONFIG_CACHE_L2_CACHE_256KB is not set'
                      '# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set'

1. CONFIG_COMPILER_OPTIMIZATION_PERF=y and disabling SIZE optimization

This makes the binary slightly larger, but in my tests it improved overall UI/display responsiveness (DSI use case).

Note: with framework-arduinoespressif32 3.3.6 I hit a linker issue when compiling in PERF mode (orphan sections ending up as separate binary segments), so I had to patch the linker script (e.g., sections.ld) to catch “orphan” .text* sections. I can share the patch/script later, or you can check my Tasmota fork (HexaOS-DEV branch).

2. CONFIG_LCD_DSI_ISR_IRAM_SAFE=y and CONFIG_LCD_DSI_ISR_CACHE_SAFE=y

For me this was crucial to prevent visible display glitches during internal flash operations (when cache can be temporarily unavailable). Keeping the relevant ISR paths IRAM-safe/cache-safe helped.

3. CONFIG_CACHE_L2_CACHE_128KB=y and CONFIG_CACHE_L2_CACHE_SIZE=0x20000

In my current setup, a larger default L2 cache size didn’t bring noticeable benefits, but it did reduce the amount of internal RAM available for other allocations (e.g., DMA-capable buffers). Reducing L2 cache to 128 KB freed up additional internal memory (roughly ~128 KB in my builds), without a measurable performance drop in my UI workload. Your mileage may vary — measure with your specific workload.

4. Touch/I²C ISR placement (CONFIG_TOUCH_CTRL_FUNC_IN_IRAM, CONFIG_TOUCH_ISR_IRAM_SAFE, CONFIG_I2C_ISR_IRAM_SAFE)

Not strictly required, but I occasionally saw flaky behavior on a shared I²C bus (touch + other devices like an RTC). Moving the touch/I²C ISR code paths to IRAM-safe sometimes improved stability.

LVGL settings (tasmota_lv_conf.h)

ESP32-P4 boards often have plenty of PSRAM, so buffer sizes are usually not the first bottleneck. Still, increasing these helped me with smoothness (less stutter, better perceived responsiveness/FPS):

#define LV_DRAW_LAYER_SIMPLE_BUF_SIZE    (4096 * 1024)
#define LV_DRAW_THREAD_STACK_SIZE    (128 * 1024)
#define LV_IMG_CACHE_DEF_SIZE_PSRAM     (8192*1024) 
#define LV_FREETYPE_CACHE_FT_GLYPH_CNT 256
#define LV_OBJ_STYLE_CACHE      1

If you’re also experimenting with ESP32-P4 and MIPI-DSI and you’ve found any useful tweaks (sdkconfig, LVGL, DMA buffers, stability fixes, etc.), please share your observations — I’d love to compare results.