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[RISC-V][MC] Introduce RVY extension feature
This adds initial features for the base RVY extension, other extensions such as the hybrid mode will be added later. Co-authored-by: Jessica Clarke <[email protected]> Co-authored-by: Alexander Richardson <[email protected]> Co-authored-by: Petr Vesely <[email protected]>
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llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ class RISCVExtensionBitmask<bits<3> groupID, int bitPos> {
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// Version of RISCVExtension to be used for Experimental extensions. This
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// sets the Experimental flag and prepends experimental- to the -mattr name.
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class RISCVExperimentalExtension<int major, int minor, string desc,
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list<RISCVExtension> implies = [],
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list<SubtargetFeature> implies = [],
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string fieldname = !subst("Feature", "Has", NAME),
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string value = "true">
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: RISCVExtension<major, minor, desc, implies, fieldname, value, true> {
@@ -1126,6 +1126,28 @@ def HasStdExtZbbOrZbkbOrP
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"'Zbkb' (Bitmanip instructions for Cryptography) or "
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"'Base P' (Packed-SIMD)">;
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// "Y" extension (CHERI support)
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def FeatureStdExtY : RISCVExperimentalExtension<0, 96, "'Base Y' (CHERI)">;
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def HasStdExtY
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: Predicate<"Subtarget->hasStdExtY()">,
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AssemblerPredicate<(all_of FeatureStdExtY), "'Base Y' (CHERI)">;
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// When enabled all memory operations (e.g. loads/stores) uses capability
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// registers as the base operand instead of the address sub-register.
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// Currently, capability mode needs to be chosen at assembly time, but follow-up
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// commits will add support for "hybrid" mode that adds instructions to
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// dynamically switch between capability mode and address mode (the latter being
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// fully backwards compatible with non-Y code).
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def FeatureCapMode : SubtargetFeature<"cap-mode", "IsCapMode", "true",
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"Capability pointer mode">;
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def IsCapMode
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: Predicate<"Subtarget->isCapMode()">,
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AssemblerPredicate<(all_of FeatureCapMode), "Capability Pointer Mode">;
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def NotCapMode : Predicate<"!Subtarget->isCapMode()">,
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AssemblerPredicate<(all_of(not FeatureCapMode)),
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"Not Capability Pointer Mode">;
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//===----------------------------------------------------------------------===//
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// Vendor extensions
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//===----------------------------------------------------------------------===//

llvm/test/MC/RISCV/invalid-attribute.s

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,8 @@
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.attribute arch, "foo"
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# CHECK: [[@LINE-1]]:18: error: invalid arch name 'foo', string must begin with rv32{i,e,g}, rv64{i,e,g}, or a supported profile name{{$}}
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.attribute arch, "rv32i2p1_y2p0"
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# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p1_y2p0', invalid standard user-level extension 'y'
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.attribute arch, "rv32i2p1_o2p0"
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# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p1_o2p0', invalid standard user-level extension 'o'
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.attribute stack_align, "16"
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# CHECK: [[@LINE-1]]:25: error: expected numeric constant

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