[RISC-V][MC] Introduce RVY extension feature

This adds initial features for the base RVY extension,
other extensions such as the hybrid mode will be added later.

Co-authored-by: Jessica Clarke <[email protected]>
Co-authored-by: Alexander Richardson <[email protected]>
Co-authored-by: Petr Vesely <[email protected]>

Author: 3 people

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -61,7 +61,7 @@ class RISCVExtensionBitmask<bits<3> groupID, int bitPos> {
 // Version of RISCVExtension to be used for Experimental extensions. This
 // sets the Experimental flag and prepends experimental- to the -mattr name.
 class RISCVExperimentalExtension<int major, int minor, string desc,
-                                 list<RISCVExtension> implies = [],
+                                 list<SubtargetFeature> implies = [],
                                  string fieldname = !subst("Feature", "Has", NAME),
                                  string value = "true">
     : RISCVExtension<major, minor, desc, implies, fieldname, value, true> {
@@ -1126,6 +1126,28 @@ def HasStdExtZbbOrZbkbOrP
                          "'Zbkb' (Bitmanip instructions for Cryptography) or "
                          "'Base P' (Packed-SIMD)">;
 
+// "Y" extension (CHERI support)
+
+def FeatureStdExtY : RISCVExperimentalExtension<0, 96, "'Base Y' (CHERI)">;
+def HasStdExtY
+    : Predicate<"Subtarget->hasStdExtY()">,
+      AssemblerPredicate<(all_of FeatureStdExtY), "'Base Y' (CHERI)">;
+
+// When enabled all memory operations (e.g. loads/stores) uses capability
+// registers as the base operand instead of the address sub-register.
+// Currently, capability mode needs to be chosen at assembly time, but follow-up
+// commits will add support for "hybrid" mode that adds instructions to
+// dynamically switch between capability mode and address mode (the latter being
+// fully backwards compatible with non-Y code).
+def FeatureCapMode : SubtargetFeature<"cap-mode", "IsCapMode", "true",
+                                      "Capability pointer mode">;
+def IsCapMode
+    : Predicate<"Subtarget->isCapMode()">,
+      AssemblerPredicate<(all_of FeatureCapMode), "Capability Pointer Mode">;
+def NotCapMode : Predicate<"!Subtarget->isCapMode()">,
+                 AssemblerPredicate<(all_of(not FeatureCapMode)),
+                                    "Not Capability Pointer Mode">;
+
 //===----------------------------------------------------------------------===//
 // Vendor extensions
 //===----------------------------------------------------------------------===//

llvm/test/MC/RISCV/invalid-attribute.s

@@ -13,8 +13,8 @@
 .attribute arch, "foo"
 # CHECK: [[@LINE-1]]:18: error: invalid arch name 'foo', string must begin with rv32{i,e,g}, rv64{i,e,g}, or a supported profile name{{$}}
 
-.attribute arch, "rv32i2p1_y2p0"
-# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p1_y2p0', invalid standard user-level extension 'y'
+.attribute arch, "rv32i2p1_o2p0"
+# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p1_o2p0', invalid standard user-level extension 'o'
 
 .attribute stack_align, "16"
 # CHECK: [[@LINE-1]]:25: error: expected numeric constant