[RISC-V][MC] Add support for RVY loads/stores

This adds supports for all new RVY loads/stores (capability-wide
versions: ly/sy instructions). Additionally, for RVY (CHERI), loads and
stores are mode-dependent, using either a YLEN register or a XLEN
register as the base.
In the former case loads/stores are authorized by that register,
and in the latter (compatibility cast), the loads/stores keep using an
address but are authorized by the DDC CSR. The assembler mnemonics are
the same in both cases. Prior to the standardization process CHERI
assembly used c-prefixed register names for capabilities, so we had the
following syntax:

lw x4, 0(c3) # capability mode: use new `CLW` instruction
lw x4, 0(x3) # integer mode: use existing `LW` instruction

During the standardization this was changed to keep the same register
name in both modes, so now we have `lw x4, 0(x3)` in both modes but we
have to select between two instructions: one using the normal GPR
register class and one using the YGPR register class.
The newly added test checks that we select the right instruction
(`LW` or `LW_Y`) using --show-inst, since both the encoding and the
assembler syntax are the same in both modes.

This commit changes the Load_ri and Store_rri tablegen classes into a
multiclass that defines the RVI and RVY at the same time to reduce the
size of the diff and hopefully improve maintainability. The downstream
fork had duplicated definitions which avoids merge conflicts but does
mean any refactorings do not make it to the almost identical duplicate
definitions. The other advantage is that we also get support for the
other load/store instructions that are not explicitly tested in this
commit.

Author: arichardson

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

@@ -735,6 +735,9 @@ static constexpr DecoderListEntry DecoderList32[]{
     {DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
     {DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
     // Standard Extensions
+    {DecoderTableRVY32Only32,
+    {RISCV::FeatureStdExtY, RISCV::Feature32Bit},
+    "RVY32-only standard 32-bit instructions"},
     {DecoderTableRVYOnly32,
      {RISCV::FeatureStdExtY},
      "RVY-only standard 32-bit instructions"},

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -227,6 +227,7 @@ def GPRMemZeroOffset : MemOperand<GPR> {
 }
 
 def GPRMem : MemOperand<GPR>;
+def YGPRMem : MemOperand<YGPR>;
 
 def SPMem : MemOperand<SP>;
 
@@ -643,9 +644,20 @@ class BranchCC_rri<bits<3> funct3, string opcodestr>
 }
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
-class Load_ri<bits<3> funct3, string opcodestr, DAGOperand rty = GPR>
-    : RVInstI<funct3, OPC_LOAD, (outs rty:$rd), (ins GPRMem:$rs1, simm12_lo:$imm12),
-              opcodestr, "$rd, ${imm12}(${rs1})">;
+multiclass Load_ri<bits<3> funct3, string opcodestr, DAGOperand rty = GPR,
+                   RISCVOpcode opcode=OPC_LOAD, list<Predicate> ExtraPreds=[],
+                   string DecoderNS=""> {
+  let DecoderNamespace = DecoderNS,
+      Predicates = !listconcat(ExtraPreds, [NotCapMode]) in
+  def "" : RVInstI<funct3, opcode, (outs rty:$rd),
+                   (ins GPRMem:$rs1, simm12_lo:$imm12), opcodestr,
+                   "$rd, ${imm12}(${rs1})">;
+  let DecoderNamespace = !if(!eq(DecoderNS, ""), "RVYOnly", !subst("RV", "RVY", DecoderNS)),
+      Predicates = !listconcat(ExtraPreds, [HasStdExtY, IsCapMode]) in
+  def _Y : RVInstI<funct3, opcode, (outs rty:$rd),
+                   (ins YGPRMem:$rs1, simm12_lo:$imm12), opcodestr,
+                   "$rd, ${imm12}(${rs1})">;
+}
 
 class HLoad_r<bits<7> funct7, bits<5> funct5, string opcodestr>
     : RVInstR<funct7, 0b100, OPC_SYSTEM, (outs GPR:$rd),
@@ -658,10 +670,19 @@ class HLoad_r<bits<7> funct7, bits<5> funct5, string opcodestr>
 // reflecting the order these fields are specified in the instruction
 // encoding.
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
-class Store_rri<bits<3> funct3, string opcodestr, DAGOperand rty = GPR>
-    : RVInstS<funct3, OPC_STORE, (outs),
+multiclass Store_rri<bits<3> funct3, string opcodestr, DAGOperand rty = GPR,
+                     list<Predicate> ExtraPreds = [], string DecoderNS = ""> {
+  let DecoderNamespace = DecoderNS,
+      Predicates = !listconcat(ExtraPreds, [NotCapMode]) in
+  def "" : RVInstS<funct3, OPC_STORE, (outs),
               (ins rty:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
               opcodestr, "$rs2, ${imm12}(${rs1})">;
+  let DecoderNamespace = !if(!eq(DecoderNS, ""), "RVYOnly", !subst("RV", "RVY", DecoderNS)),
+      Predicates = !listconcat(ExtraPreds, [HasStdExtY, IsCapMode]) in
+  def _Y : RVInstS<funct3, OPC_STORE, (outs),
+                   (ins rty:$rs2, YGPRMem:$rs1, simm12_lo:$imm12),
+                   opcodestr, "$rs2, ${imm12}(${rs1})">;
+}
 
 class HStore_rr<bits<7> funct7, string opcodestr>
     : RVInstR<funct7, 0b100, OPC_SYSTEM, (outs),
@@ -769,16 +790,16 @@ def BLTU : BranchCC_rri<0b110, "bltu">;
 def BGEU : BranchCC_rri<0b111, "bgeu">;
 
 let IsSignExtendingOpW = 1 in {
-def LB  : Load_ri<0b000, "lb">, Sched<[WriteLDB, ReadMemBase]>;
-def LH  : Load_ri<0b001, "lh">, Sched<[WriteLDH, ReadMemBase]>;
-def LW  : Load_ri<0b010, "lw">, Sched<[WriteLDW, ReadMemBase]>;
-def LBU : Load_ri<0b100, "lbu">, Sched<[WriteLDB, ReadMemBase]>;
-def LHU : Load_ri<0b101, "lhu">, Sched<[WriteLDH, ReadMemBase]>;
+defm LB  : Load_ri<0b000, "lb">, Sched<[WriteLDB, ReadMemBase]>;
+defm LH  : Load_ri<0b001, "lh">, Sched<[WriteLDH, ReadMemBase]>;
+defm LW  : Load_ri<0b010, "lw">, Sched<[WriteLDW, ReadMemBase]>;
+defm LBU : Load_ri<0b100, "lbu">, Sched<[WriteLDB, ReadMemBase]>;
+defm LHU : Load_ri<0b101, "lhu">, Sched<[WriteLDH, ReadMemBase]>;
 }
 
-def SB : Store_rri<0b000, "sb">, Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
-def SH : Store_rri<0b001, "sh">, Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
-def SW : Store_rri<0b010, "sw">, Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
+defm SB : Store_rri<0b000, "sb">, Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
+defm SH : Store_rri<0b001, "sh">, Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
+defm SW : Store_rri<0b010, "sw">, Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
 
 // ADDI isn't always rematerializable, but isReMaterializable will be used as
 // a hint which is verified in isReMaterializableImpl.
@@ -888,11 +909,14 @@ def CSRRCI : CSR_ii<0b111, "csrrci">;
 
 /// RV64I instructions
 
-let Predicates = [IsRV64] in {
-def LWU   : Load_ri<0b110, "lwu">, Sched<[WriteLDW, ReadMemBase]>;
-def LD    : Load_ri<0b011, "ld">, Sched<[WriteLDD, ReadMemBase]>;
-def SD    : Store_rri<0b011, "sd">, Sched<[WriteSTD, ReadStoreData, ReadMemBase]>;
+defm LWU   : Load_ri<0b110, "lwu", ExtraPreds=[IsRV64]>,
+             Sched<[WriteLDW, ReadMemBase]>;
+defm LD    : Load_ri<0b011, "ld", ExtraPreds=[IsRV64]>,
+             Sched<[WriteLDD, ReadMemBase]>;
+defm SD    : Store_rri<0b011, "sd", ExtraPreds=[IsRV64]>,
+             Sched<[WriteSTD, ReadStoreData, ReadMemBase]>;
 
+let Predicates = [IsRV64] in {
 let IsSignExtendingOpW = 1 in {
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def ADDIW : RVInstI<0b000, OPC_OP_IMM_32, (outs GPR:$rd),

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

@@ -337,15 +337,16 @@ def FLW : FPLoad_r<0b010, "flw", FPR32, WriteFLD32>;
 def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
 } // Predicates = [HasStdExtF]
 
-let Predicates = [HasStdExtZfinx], isCodeGenOnly = 1 in {
-def LW_INX : Load_ri<0b010, "lw", GPRF32>, Sched<[WriteLDW, ReadMemBase]>;
-def SW_INX : Store_rri<0b010, "sw", GPRF32>,
+let isCodeGenOnly = 1 in {
+defm LW_INX : Load_ri<0b010, "lw", GPRF32, ExtraPreds=[HasStdExtZfinx]>,
+              Sched<[WriteLDW, ReadMemBase]>;
+defm SW_INX : Store_rri<0b010, "sw", GPRF32, ExtraPreds=[HasStdExtZfinx]>,
              Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
 
 // ADDI with GPRF32 register class to use for copy. This should not be used as
 // general ADDI, so the immediate should always be zero.
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveReg = 1,
-    hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+    hasSideEffects = 0, mayLoad = 0, mayStore = 0, Predicates=[HasStdExtZfinx] in
 def PseudoMV_FPR32INX : Pseudo<(outs GPRF32:$rd), (ins GPRF32:$rs), []>,
                         Sched<[WriteIALU, ReadIALU]>;
 }

llvm/lib/Target/RISCV/RISCVInstrInfoY.td

@@ -107,3 +107,9 @@ let Predicates = [HasStdExtY] in {
   def YLT : RVY_rr<0x6, 0x6, "ylt", GPR, YGPR, YGPR>;
   def YAMASK : RVY_r<0x7, "yamask", GPR, GPR>;
 } // Predicates = [HasStdExtY]
+
+// Instructions to Load and Store Capability Data
+defm LY : Load_ri<0b100, "ly", opcode=OPC_MISC_MEM, ExtraPreds=[HasStdExtY]>,
+          Sched<[/* TODO: WriteLDY, */ ReadMemBase]>;
+defm SY : Store_rri<0b100, "sy", ExtraPreds=[HasStdExtY]>,
+          Sched<[/* TODO: WriteSTY, */ ReadStoreData, ReadMemBase]>;

llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

@@ -98,15 +98,17 @@ def FLH : FPLoad_r<0b001, "flh", FPR16, WriteFLD16>;
 def FSH : FPStore_r<0b001, "fsh", FPR16, WriteFST16>;
 } // Predicates = [HasHalfFPLoadStoreMove]
 
-let Predicates = [HasStdExtZhinxmin], isCodeGenOnly = 1 in {
-def LH_INX : Load_ri<0b001, "lh", GPRF16>, Sched<[WriteLDH, ReadMemBase]>;
-def SH_INX : Store_rri<0b001, "sh", GPRF16>,
-             Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
+let isCodeGenOnly = 1 in {
+defm LH_INX : Load_ri<0b001, "lh", GPRF16, ExtraPreds=[HasStdExtZfinx]>,
+              Sched<[WriteLDH, ReadMemBase]>;
+defm SH_INX : Store_rri<0b001, "sh", GPRF16, ExtraPreds=[HasStdExtZfinx]>,
+              Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
 
 // ADDI with GPRF16 register class to use for copy. This should not be used as
 // general ADDI, so the immediate should always be zero.
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveReg = 1,
-    hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+    hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+    Predicates = [HasStdExtZhinxmin] in
 def PseudoMV_FPR16INX : Pseudo<(outs GPRF16:$rd), (ins GPRF16:$rs), []>,
                         Sched<[WriteIALU, ReadIALU]>;
 }

llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td

@@ -33,11 +33,12 @@ def riscv_st_rv32 : RVSDNode<"SD_RV32", SDT_RISCV_SD_RV32,
 // Instructions
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtZilsd, IsRV32], DecoderNamespace = "RV32Only" in {
-def LD_RV32 : Load_ri<0b011, "ld", GPRPairRV32>, Sched<[WriteLDD, ReadMemBase]>;
-def SD_RV32 : Store_rri<0b011, "sd", GPRPairRV32>,
-              Sched<[WriteSTD, ReadStoreData, ReadMemBase]>;
-} // Predicates = [HasStdExtZilsd, IsRV32], DecoderNamespace = "RV32Only"
+defm LD_RV32 : Load_ri<0b011, "ld", GPRPairRV32, DecoderNS="RV32Only",
+                       ExtraPreds=[HasStdExtZilsd, IsRV32]>,
+               Sched<[WriteLDD, ReadMemBase]>;
+defm SD_RV32 : Store_rri<0b011, "sd", GPRPairRV32, DecoderNS="RV32Only",
+                         ExtraPreds=[HasStdExtZilsd, IsRV32]>,
+               Sched<[WriteSTD, ReadStoreData, ReadMemBase]>;
 
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions

llvm/lib/Target/RISCV/RISCVSchedule.td

@@ -27,11 +27,13 @@ def WriteLDB        : SchedWrite;    // Load byte
 def WriteLDH        : SchedWrite;    // Load half-word
 def WriteLDW        : SchedWrite;    // Load word
 def WriteLDD        : SchedWrite;    // Load double-word
+// TODO: def WriteLDY        : SchedWrite;    // Load capability
 def WriteCSR        : SchedWrite;    // CSR instructions
 def WriteSTB        : SchedWrite;    // Store byte
 def WriteSTH        : SchedWrite;    // Store half-word
 def WriteSTW        : SchedWrite;    // Store word
 def WriteSTD        : SchedWrite;    // Store double-word
+// TODO: def WriteSTY        : SchedWrite;    // Store capability
 def WriteAtomicB    : SchedWrite;    //Atomic memory operation byte size
 def WriteAtomicH    : SchedWrite;    //Atomic memory operation halfword size
 def WriteAtomicW    : SchedWrite;    //Atomic memory operation word size

llvm/test/MC/RISCV/rvy/rvy-valid-load-store.s

@@ -0,0 +1,78 @@
+# RUN: llvm-mc %s --triple=riscv32 -mattr=+experimental-y --riscv-no-aliases --show-encoding --show-inst \
+# RUN:   | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ -DSUFFIX= %s
+# RUN: llvm-mc %s --triple=riscv32 -mattr=+experimental-y,+cap-mode --riscv-no-aliases --show-encoding --show-inst \
+# RUN:   | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ -DSUFFIX=_Y %s
+# RUN: llvm-mc --filetype=obj --triple=riscv32 --mattr=+experimental-y < %s \
+# RUN:   | llvm-objdump --mattr=+experimental-y -M no-aliases -d --no-print-imm-hex - \
+# RUN:   | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+#
+# RUN: llvm-mc %s --triple=riscv64 --mattr=+experimental-y --riscv-no-aliases \
+# RUN:   --show-encoding --show-inst --defsym=RV64=1 \
+# RUN:   | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-64,CHECK-ASM-AND-OBJ,CHECK-ASM-AND-OBJ-64 -DSUFFIX= %s
+# RUN: llvm-mc %s --triple=riscv64 --mattr=+experimental-y,+cap-mode --riscv-no-aliases \
+# RUN:   --show-encoding --show-inst --defsym=RV64=1 \
+# RUN:   | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-64,CHECK-ASM-AND-OBJ,CHECK-ASM-AND-OBJ-64 -DSUFFIX=_Y %s
+# RUN: llvm-mc --filetype=obj --triple=riscv64 --mattr=+experimental-y \
+# RUN:   --riscv-no-aliases --show-encoding --defsym=RV64=1 < %s \
+# RUN:   | llvm-objdump --mattr=+experimental-y -M no-aliases -d --no-print-imm-hex - \
+# RUN:   | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ,CHECK-ASM-AND-OBJ-64 %s
+
+## Both capability normal RISC-V instruction use the same encoding, but we have
+## to check that we select the correct MCInst: for +cap-mode we want a _Y suffix
+
+# CHECK-ASM-AND-OBJ: lb	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x03,0x85,0x05,0x00]
+# CHECK-ASM-NEXT: <MCInst #[[#]] LB[[SUFFIX]]{{$}}
+lb a0, 0(a1)
+# CHECK-ASM-AND-OBJ: sb	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x23,0x80,0xa5,0x00]
+# CHECK-ASM-NEXT: <MCInst #[[#]] SB[[SUFFIX]]{{$}}
+sb a0, 0(a1)
+# CHECK-ASM-AND-OBJ: lbu	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x03,0xc5,0x05,0x00]
+# CHECK-ASM-NEXT: <MCInst #[[#]] LBU[[SUFFIX]]{{$}}
+lbu a0, 0(a1)
+# CHECK-ASM-AND-OBJ: lh	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x03,0x95,0x05,0x00]
+# CHECK-ASM-NEXT: <MCInst #[[#]] LH[[SUFFIX]]{{$}}
+lh a0, 0(a1)
+# CHECK-ASM-AND-OBJ: sh	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x23,0x90,0xa5,0x00]
+# CHECK-ASM-NEXT: <MCInst #[[#]] SH[[SUFFIX]]{{$}}
+sh a0, 0(a1)
+# CHECK-ASM-AND-OBJ: lhu	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x03,0xd5,0x05,0x00]
+# CHECK-ASM-NEXT: <MCInst #[[#]] LHU[[SUFFIX]]{{$}}
+lhu a0, 0(a1)
+# CHECK-ASM-AND-OBJ: lw	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x03,0xa5,0x05,0x00]
+# CHECK-ASM-NEXT: <MCInst #[[#]] LW[[SUFFIX]]{{$}}
+lw a0, 0(a1)
+# CHECK-ASM-AND-OBJ: sw	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x23,0xa0,0xa5,0x00]
+# CHECK-ASM-NEXT: <MCInst #[[#]] SW[[SUFFIX]]{{$}}
+sw a0, 0(a1)
+
+.ifdef RV64
+# CHECK-ASM-AND-OBJ-64: lwu	a0, 0(a1)
+# CHECK-ASM-64-SAME: # encoding: [0x03,0xe5,0x05,0x00]
+# CHECK-ASM-64-NEXT: <MCInst #[[#]] LWU[[SUFFIX]]{{$}}
+lwu a0, 0(a1)
+# CHECK-ASM-AND-OBJ-64: ld	a0, 0(a1)
+# CHECK-ASM-64-SAME: # encoding: [0x03,0xb5,0x05,0x00]
+# CHECK-ASM-64-NEXT: <MCInst #[[#]] LD[[SUFFIX]]{{$}}
+ld a0, 0(a1)
+# CHECK-ASM-AND-OBJ-64: sd	a0, 0(a1)
+# CHECK-ASM-64-SAME: # encoding: [0x23,0xb0,0xa5,0x00]
+# CHECK-ASM-64-NEXT: <MCInst #[[#]] SD[[SUFFIX]]{{$}}
+sd a0, 0(a1)
+.endif
+
+# CHECK-ASM-AND-OBJ: ly	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x0f,0xc5,0x05,0x00]
+# CHECK-ASM-NEXT: <MCInst #[[#]] LY[[SUFFIX]]{{$}}
+ly a0, 0(a1)
+# CHECK-ASM-AND-OBJ: sy	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x23,0xc0,0xa5,0x00]
+# CHECK-ASM-NEXT: <MCInst #[[#]] SY[[SUFFIX]]{{$}}
+sy a0, 0(a1)