[RISC-V][MC] Add support for RVY loads/stores

This adds supports for all new RVY loads/stores (capability-wide
versions: ly/sy instructions). Additionally, for RVY (CHERI), loads and
stores are mode-dependent, using either a YLEN register or a XLEN
register as the base.
In the former case loads/stores are authorized by that register,
and in the latter (compatibility mode), the loads/stores keep using an
address but are authorized by the DDC CSR. The assembler mnemonics are
the same in both cases. Prior to the standardization process CHERI
assembly used c-prefixed register names for capabilities, so we had the
following syntax:

lw x4, 0(c3) # capability mode: use new `CLW` instruction
lw x4, 0(x3) # integer mode: use existing `LW` instruction

During the standardization this was changed to keep the same register
name in both modes, so now we have `lw x4, 0(x3)` in both modes.

This allows using the RegClassByHwMode feature to reuse the same MC
instruction but with a different operand type depending on the HwMode.
The downstream fork had duplicated definitions which meant a lot of
switch statements now needed to handle both MCInsts. This approach
using HwMode should be much more maintainable and only introduces a
minor diff compared to what we had downstream.
This will also make it much easier adding support for RVY versions of
other extensions such as vector, since we just need to change out the
`GPRMem` operand with `PtrMem`.

Author: arichardson

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -1367,7 +1367,14 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
   bool IsRegFPR64C =
       RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg);
   bool IsRegVR = RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg);
-  if (Op.isGPR() && Kind == MCK_YGPR) {
+
+  // In RVY mode, the MemPtrRC register class should select capability registers
+  // for the base pointer operands, otherwise we use GPRs.
+  // TODO: Is there any way we could do this in tablegen automatically?
+  if (Kind == MCK_RegByHwMode_MemPtrRC)
+    Kind = STI->hasFeature(RISCV::FeatureCapMode) ? MCK_YGPR : MCK_GPR;
+
+  if (Op.isGPR() && (Kind == MCK_YGPR)) {
     // GPR and capability GPR use the same register names, convert if required.
     Op.Reg.Reg = convertGPRToYGPR(Reg);
     return Match_Success;

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -1774,8 +1774,10 @@ def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
              AssemblerPredicate<(all_of (not Feature64Bit)),
                                 "RV32I Base Instruction Set">;
 
-defvar RV32 = DefaultMode;
-def RV64 : HwMode<[IsRV64]>;
+def RV32I : HwMode<[IsRV32, NotCapMode]>;
+def RV64I : HwMode<[IsRV64, NotCapMode]>;
+def RV32Y : HwMode<[IsRV32, IsCapMode]>;
+def RV64Y : HwMode<[IsRV64, IsCapMode]>;
 
 def FeatureRelax
     : SubtargetFeature<"relax", "EnableLinkerRelax", "true",

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -217,7 +217,7 @@ def ZeroOffsetMemOpOperand : AsmOperandClass {
   let ParserMethod = "parseZeroOffsetMemOp";
 }
 
-class MemOperand<RegisterClass regClass> : RegisterOperand<regClass>{
+class MemOperand<RegisterClassLike regClass> : RegisterOperand<regClass> {
   let OperandType = "OPERAND_MEMORY";
 }
 
@@ -227,6 +227,14 @@ def GPRMemZeroOffset : MemOperand<GPR> {
 }
 
 def GPRMem : MemOperand<GPR>;
+def YGPRMem : MemOperand<YGPR>;
+
+def MemPtrRC : RegClassByHwMode<
+  [RV32I, RV64I, RV32Y, RV64Y],
+  [GPR, GPR, YGPR, YGPR]>;
+
+def PtrMem : MemOperand<MemPtrRC>;
+
 
 def SPMem : MemOperand<SP>;
 
@@ -643,8 +651,9 @@ class BranchCC_rri<bits<3> funct3, string opcodestr>
 }
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
-class Load_ri<bits<3> funct3, string opcodestr, DAGOperand rty = GPR>
-    : RVInstI<funct3, OPC_LOAD, (outs rty:$rd), (ins GPRMem:$rs1, simm12_lo:$imm12),
+class Load_ri<bits<3> funct3, string opcodestr, DAGOperand rty = GPR,
+              RISCVOpcode opcode = OPC_LOAD>
+    : RVInstI<funct3, opcode, (outs rty:$rd), (ins PtrMem:$rs1, simm12_lo:$imm12),
               opcodestr, "$rd, ${imm12}(${rs1})">;
 
 class HLoad_r<bits<7> funct7, bits<5> funct5, string opcodestr>
@@ -660,7 +669,7 @@ class HLoad_r<bits<7> funct7, bits<5> funct5, string opcodestr>
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
 class Store_rri<bits<3> funct3, string opcodestr, DAGOperand rty = GPR>
     : RVInstS<funct3, OPC_STORE, (outs),
-              (ins rty:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
+              (ins rty:$rs2, PtrMem:$rs1, simm12_lo:$imm12),
               opcodestr, "$rs2, ${imm12}(${rs1})">;
 
 class HStore_rr<bits<7> funct7, string opcodestr>
@@ -1164,22 +1173,22 @@ let Predicates = [HasStdExtZihintntl] in {
 
 let EmitPriority = 0 in {
 def : InstAlias<"lb $rd, (${rs1})",
-                (LB  GPR:$rd, GPR:$rs1, 0)>;
+                (LB  GPR:$rd, PtrMem:$rs1, 0)>;
 def : InstAlias<"lh $rd, (${rs1})",
-                (LH  GPR:$rd, GPR:$rs1, 0)>;
+                (LH  GPR:$rd, PtrMem:$rs1, 0)>;
 def : InstAlias<"lw $rd, (${rs1})",
-                (LW  GPR:$rd, GPR:$rs1, 0)>;
+                (LW  GPR:$rd, PtrMem:$rs1, 0)>;
 def : InstAlias<"lbu $rd, (${rs1})",
-                (LBU  GPR:$rd, GPR:$rs1, 0)>;
+                (LBU  GPR:$rd, PtrMem:$rs1, 0)>;
 def : InstAlias<"lhu $rd, (${rs1})",
-                (LHU  GPR:$rd, GPR:$rs1, 0)>;
+                (LHU  GPR:$rd, PtrMem:$rs1, 0)>;
 
 def : InstAlias<"sb $rs2, (${rs1})",
-                (SB  GPR:$rs2, GPR:$rs1, 0)>;
+                (SB  GPR:$rs2, PtrMem:$rs1, 0)>;
 def : InstAlias<"sh $rs2, (${rs1})",
-                (SH  GPR:$rs2, GPR:$rs1, 0)>;
+                (SH  GPR:$rs2, PtrMem:$rs1, 0)>;
 def : InstAlias<"sw $rs2, (${rs1})",
-                (SW  GPR:$rs2, GPR:$rs1, 0)>;
+                (SW  GPR:$rs2, PtrMem:$rs1, 0)>;
 
 def : InstAlias<"add $rd, $rs1, $imm12",
                 (ADDI  GPR:$rd, GPR:$rs1, simm12_lo:$imm12)>;
@@ -1197,11 +1206,11 @@ def : InstAlias<"sra $rd, $rs1, $shamt",
                 (SRAI  GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
 let Predicates = [IsRV64] in {
 def : InstAlias<"lwu $rd, (${rs1})",
-                (LWU  GPR:$rd, GPR:$rs1, 0)>;
+                (LWU  GPR:$rd, PtrMem:$rs1, 0)>;
 def : InstAlias<"ld $rd, (${rs1})",
-                (LD  GPR:$rd, GPR:$rs1, 0)>;
+                (LD  GPR:$rd, PtrMem:$rs1, 0)>;
 def : InstAlias<"sd $rs2, (${rs1})",
-                (SD  GPR:$rs2, GPR:$rs1, 0)>;
+                (SD  GPR:$rs2, PtrMem:$rs1, 0)>;
 
 def : InstAlias<"addw $rd, $rs1, $imm12",
                 (ADDIW  GPR:$rd, GPR:$rs1, simm12_lo:$imm12)>;

llvm/lib/Target/RISCV/RISCVInstrInfoY.td

@@ -106,4 +106,11 @@ let Predicates = [HasStdExtY] in {
   def SYEQ : RVY_rr<0x6, 0x4, "syeq", GPR, YGPR, YGPR>;
   def YLT : RVY_rr<0x6, 0x6, "ylt", GPR, YGPR, YGPR>;
   def YAMASK : RVY_r<0x7, "yamask", GPR, GPR>;
+
+  // Instructions to Load and Store Capability Data
+  def LY : Load_ri<0b100, "ly", opcode=OPC_MISC_MEM>,
+           Sched<[/* TODO: WriteLDY, */ ReadMemBase]>;
+  def SY : Store_rri<0b100, "sy">,
+           Sched<[/* TODO: WriteSTY, */ ReadStoreData, ReadMemBase]>;
+
 } // Predicates = [HasStdExtY]

llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td

@@ -47,6 +47,6 @@ let Predicates = [HasStdExtZilsd, IsRV32] in {
 def PseudoLD_RV32 : PseudoLoad<"ld", GPRPairRV32>;
 def PseudoSD_RV32 : PseudoStore<"sd", GPRPairRV32>;
 
-def : InstAlias<"ld $rd, (${rs1})", (LD_RV32 GPRPairRV32:$rd, GPR:$rs1, 0), 0>;
-def : InstAlias<"sd $rs2, (${rs1})", (SD_RV32 GPRPairRV32:$rs2, GPR:$rs1, 0), 0>;
+def : InstAlias<"ld $rd, (${rs1})", (LD_RV32 GPRPairRV32:$rd, PtrMem:$rs1, 0), 0>;
+def : InstAlias<"sd $rs2, (${rs1})", (SD_RV32 GPRPairRV32:$rs2, PtrMem:$rs1, 0), 0>;
 }

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

@@ -55,8 +55,9 @@ class RISCVReg128<RISCVReg64 subreg>
 // A subreg index for the address part of capability registers (this is just the
 // default XLEN-wide X<N> register).
 def sub_cap_addr : SubRegIndex<32> {
-  let SubRegRanges =
-      SubRegRangeByHwMode<[RV32, RV64], [SubRegRange<32>, SubRegRange<64>]>;
+  let SubRegRanges = SubRegRangeByHwMode<
+    [RV32I, RV64I, RV32Y, RV64Y],
+    [SubRegRange<32>, SubRegRange<64>, SubRegRange<32>, SubRegRange<64>]>;
 }
 class RISCVCapReg<RISCVRegWithSubRegs subreg, string n, list<string> alt = []>
     : RISCVRegWithSubRegs<subreg.HWEncoding{4 -0}, n, [subreg], alt> {
@@ -83,12 +84,14 @@ def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>;
 
 // GPR sizes change with HwMode.
 def sub_gpr_even : SubRegIndex<32> {
-  let SubRegRanges = SubRegRangeByHwMode<[RV32, RV64],
-                                         [SubRegRange<32>, SubRegRange<64>]>;
+  let SubRegRanges = SubRegRangeByHwMode<
+    [RV32I, RV64I, RV32Y, RV64Y],
+    [SubRegRange<32>, SubRegRange<32>, SubRegRange<64>, SubRegRange<64>]>;
 }
 def sub_gpr_odd  : SubRegIndex<32, 32> {
-  let SubRegRanges = SubRegRangeByHwMode<[RV32, RV64],
-                                         [SubRegRange<32, 32>, SubRegRange<64, 64>]>;
+  let SubRegRanges = SubRegRangeByHwMode<
+    [RV32I, RV64I, RV32Y, RV64Y],
+    [SubRegRange<32, 32>, SubRegRange<32, 32>, SubRegRange<64, 64>, SubRegRange<64, 64>]>;
 }
 } // Namespace = "RISCV"
 
@@ -264,27 +267,32 @@ let RegAltNameIndices = [ABIRegAltName] in {
   }
 }
 
-def XLenVT : ValueTypeByHwMode<[RV32, RV64],
-                               [i32,  i64]>;
+def XLenVT : ValueTypeByHwMode<[RV32I, RV64I, RV32Y, RV64Y],
+                               [i32,   i64,   i32,   i64]>;
 defvar XLenPairVT = untyped;
 
 // Allow f64 in GPR for ZDINX on RV64.
-def XLenFVT : ValueTypeByHwMode<[RV64],
-                                [f64]>;
-def XLenPairFVT : ValueTypeByHwMode<[RV32],
-                                    [f64]>;
+def XLenFVT : ValueTypeByHwMode<[RV64I, RV64Y],
+                                [f64,   f64]>;
+def XLenPairFVT : ValueTypeByHwMode<[RV32I, RV32Y],
+                                    [f64,   f64]>;
 
 // P extension
-def XLenVecI8VT : ValueTypeByHwMode<[RV32, RV64],
-                                    [v4i8, v8i8]>;
-def XLenVecI16VT : ValueTypeByHwMode<[RV32,  RV64],
-                                     [v2i16, v4i16]>;
+def XLenVecI8VT : ValueTypeByHwMode<[RV32I, RV64I, RV32Y, RV64Y],
+                                    [v4i8,  v8i8,  v4i8,  v8i8]>;
+def XLenVecI16VT : ValueTypeByHwMode<[RV32I, RV64I, RV32Y, RV64Y],
+                                     [v2i16, v4i16, v2i16, v4i16]>;
 def XLenRI : RegInfoByHwMode<
-      [RV32,              RV64],
-      [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
-def YLenVT : ValueTypeByHwMode<[RV32, RV64], [c64, c128]>;
-def YLenRI : RegInfoByHwMode<[RV32, RV64], [RegInfo<64, 64, 64>,
-                                            RegInfo<128, 128, 128>]>;
+      [RV32I,             RV64I,             RV32Y,             RV64Y],
+      [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>, RegInfo<64,64,64>]>;
+def YLenVT : ValueTypeByHwMode<[RV32I, RV64I, RV32Y, RV64Y],
+                               [c64,   c128,  c64,   c128]>;
+def YLenRI : RegInfoByHwMode<
+      [RV32I,               RV64I,                  RV32Y,               RV64Y],
+      [RegInfo<64, 64, 64>, RegInfo<128, 128, 128>, RegInfo<64, 64, 64>, RegInfo<128, 128, 128>]>;
+
+def PtrLenVT : ValueTypeByHwMode<[RV32I, RV64I, RV32Y, RV64Y],
+                                 [i32,   i64,   c64,   c128]>;
 
 class RISCVRegisterClass<list<ValueType> regTypes, int align, dag regList>
     : RegisterClass<"RISCV", regTypes, align, regList> {
@@ -394,8 +402,8 @@ def GPRNoX31 : GPRRegisterClass<(sub GPR, X31)> {
 //===----------------------------------------------------------------------===//
 
 def XLenPairRI : RegInfoByHwMode<
-      [RV32,                RV64],
-      [RegInfo<64, 64, 32>, RegInfo<128, 128, 64>]>;
+      [RV32I,               RV64I,                 RV32Y,               RV64Y],
+      [RegInfo<64, 64, 32>, RegInfo<128, 128, 64>, RegInfo<64, 64, 32>, RegInfo<128, 128, 64>]>;
 
 // Dummy zero register for use in the register pair containing X0 (as X1 is
 // not read to or written when the X0 register pair is used).

llvm/lib/Target/RISCV/RISCVSchedule.td

@@ -27,11 +27,13 @@ def WriteLDB        : SchedWrite;    // Load byte
 def WriteLDH        : SchedWrite;    // Load half-word
 def WriteLDW        : SchedWrite;    // Load word
 def WriteLDD        : SchedWrite;    // Load double-word
+// TODO: def WriteLDY        : SchedWrite;    // Load capability
 def WriteCSR        : SchedWrite;    // CSR instructions
 def WriteSTB        : SchedWrite;    // Store byte
 def WriteSTH        : SchedWrite;    // Store half-word
 def WriteSTW        : SchedWrite;    // Store word
 def WriteSTD        : SchedWrite;    // Store double-word
+// TODO: def WriteSTY        : SchedWrite;    // Store capability
 def WriteAtomicB    : SchedWrite;    //Atomic memory operation byte size
 def WriteAtomicH    : SchedWrite;    //Atomic memory operation halfword size
 def WriteAtomicW    : SchedWrite;    //Atomic memory operation word size

llvm/test/MC/RISCV/rvy/rvy-valid-load-store.s

@@ -0,0 +1,65 @@
+# RUN: llvm-mc %s --triple=riscv32 -mattr=+experimental-y --riscv-no-aliases --show-encoding \
+# RUN:   | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s --triple=riscv32 -mattr=+experimental-y,+cap-mode --riscv-no-aliases --show-encoding \
+# RUN:   | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc --filetype=obj --triple=riscv32 --mattr=+experimental-y < %s \
+# RUN:   | llvm-objdump --mattr=+experimental-y -M no-aliases -d --no-print-imm-hex - \
+# RUN:   | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+#
+# RUN: llvm-mc %s --triple=riscv64 --mattr=+experimental-y --riscv-no-aliases \
+# RUN:   --show-encoding --defsym=RV64=1 \
+# RUN:   | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-64,CHECK-ASM-AND-OBJ,CHECK-ASM-AND-OBJ-64 %s
+# RUN: llvm-mc %s --triple=riscv64 --mattr=+experimental-y,+cap-mode --riscv-no-aliases \
+# RUN:   --show-encoding --defsym=RV64=1 \
+# RUN:   | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-64,CHECK-ASM-AND-OBJ,CHECK-ASM-AND-OBJ-64 %s
+# RUN: llvm-mc --filetype=obj --triple=riscv64 --mattr=+experimental-y \
+# RUN:   --riscv-no-aliases --show-encoding --defsym=RV64=1 < %s \
+# RUN:   | llvm-objdump --mattr=+experimental-y -M no-aliases -d --no-print-imm-hex - \
+# RUN:   | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ,CHECK-ASM-AND-OBJ-64 %s
+
+## Both capability & normal RISC-V instruction use the same encoding, and the
+## same MCInst as we rely on RegClassByHwMode to select the rigt base pointer.
+
+# CHECK-ASM-AND-OBJ: lb	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x03,0x85,0x05,0x00]
+lb a0, 0(a1)
+# CHECK-ASM-AND-OBJ: sb	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x23,0x80,0xa5,0x00]
+sb a0, 0(a1)
+# CHECK-ASM-AND-OBJ: lbu	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x03,0xc5,0x05,0x00]
+lbu a0, 0(a1)
+# CHECK-ASM-AND-OBJ: lh	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x03,0x95,0x05,0x00]
+lh a0, 0(a1)
+# CHECK-ASM-AND-OBJ: sh	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x23,0x90,0xa5,0x00]
+sh a0, 0(a1)
+# CHECK-ASM-AND-OBJ: lhu	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x03,0xd5,0x05,0x00]
+lhu a0, 0(a1)
+# CHECK-ASM-AND-OBJ: lw	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x03,0xa5,0x05,0x00]
+lw a0, 0(a1)
+# CHECK-ASM-AND-OBJ: sw	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x23,0xa0,0xa5,0x00]
+sw a0, 0(a1)
+
+.ifdef RV64
+# CHECK-ASM-AND-OBJ-64: lwu	a0, 0(a1)
+# CHECK-ASM-64-SAME: # encoding: [0x03,0xe5,0x05,0x00]
+lwu a0, 0(a1)
+# CHECK-ASM-AND-OBJ-64: ld	a0, 0(a1)
+# CHECK-ASM-64-SAME: # encoding: [0x03,0xb5,0x05,0x00]
+ld a0, 0(a1)
+# CHECK-ASM-AND-OBJ-64: sd	a0, 0(a1)
+# CHECK-ASM-64-SAME: # encoding: [0x23,0xb0,0xa5,0x00]
+sd a0, 0(a1)
+.endif
+
+# CHECK-ASM-AND-OBJ: ly	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x0f,0xc5,0x05,0x00]
+ly a0, 0(a1)
+# CHECK-ASM-AND-OBJ: sy	a0, 0(a1)
+# CHECK-ASM-SAME: # encoding: [0x23,0xc0,0xa5,0x00]
+sy a0, 0(a1)