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1 parent a7ca187 commit e97a53fCopy full SHA for e97a53f
llvm/test/MC/RISCV/rvy/rv32y-invalid-mode-independent.s
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-# RUN: not llvm-mc --triple riscv32 --mattr=+experimental-y <%s
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# RUN: not llvm-mc --triple riscv32 --mattr=+experimental-y <%s 2>&1 \
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# RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-32 '--implicit-check-not=error:'
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# RUN: not llvm-mc --triple riscv64 --mattr=+experimental-y <%s 2>&1 \
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