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Merge pull request #151 from arm-university/main
Challenge page updates and early draft proj
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‎Projects/Projects/HLS4ML-AI-SoC_Design.md‎

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---
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title: "HLS4ML - AI SoC Design"
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description: "Explore using HLS4ML, an open-source project developed at organisations including CERN, Fermilab, and MIT, to create hardware for AI, compatible with Arm IP to form an SoC capable of tape-out."
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subjects:
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- "ML"
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- "Performance and Architecture"
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requires-team:
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- "No"
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platform:
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- "AI"
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sw-hw:
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- "Software"
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- "Hardware"
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support-level:
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- "Self-Service"
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- "Arm Ambassador Support"
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publication-date: 2026-01-16
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license:
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status:
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- "Hidden"
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---
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![learn_on_arm](../../images/Learn_on_Arm_banner.png)
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# SoC Labs Logo
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## Description
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### Why is this important?
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Tools such as HLS4ML have proven extremely successful for rapid FPGA-based AI acceleration, particularly in research and edge-AI contexts. However, there is currently a significant gap between FPGA-targeted HLS workflows and reproducible, tape-out-ready ASIC design flows.
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Many AI accelerator projects focus on a single model, dataset, or hardware target. This project instead focuses on defining a repeatable and auditable methodology for translating AI models into hardware IP suitable for integration into an Arm-based SoC and potential fabrication.
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We are looking for a clear, well-documented path from AI model → HLS → RTL → Arm-based SoC → tape-out. This reduces the cost, risk, and expertise barrier for startups, academics, and independent developers to innovate on silicon.
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### Project Summary
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This project explores the use of HLS4ML (and comparable HLS-based AI tools) to develop a repeatable, tape-out-capable workflow for creating AI accelerator IP that can be integrated with Arm IP into a full SoC design.
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The focus is not on a single accelerator or model, but on defining a methodology that includes:
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AI and software layer
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- Selection of AI models (e.g. CNNs, transformers, or classical ML models).
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- Quantisation, pruning, and model optimisation strategies compatible with hardware implementation.
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- Clear mapping between software frameworks (e.g. TensorFlow / PyTorch) and hardware-friendly representations.
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Hardware generation layer
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- Use of HLS4ML (or alternatives where appropriate) to generate synthesizable RTL.
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- Identification of constraints and modifications required to move from FPGA-oriented HLS outputs to ASIC-suitable RTL.
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- Definition of design rules, interfaces, and verification steps that ensure reproducibility.
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SoC Design
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- Integration of the generated accelerator as an IP block within an Arm-based SoC.
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- Documentation of the additional steps required beyond FPGA validation: synthesis targets, timing closure considerations, verification, and power/area trade-offs.
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- Clear identification of what changes are needed to move from “works on FPGA” to “ready for fabrication”.
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The output of this project is a reference flow, example designs, and documentation that others can follow to reproducibly generate AI accelerator IP suitable for integration into real Arm-based silicon.
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## What will you use?
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You should be familiar with, or willing to learn about:
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- High-level Synthesis (HLS), including HLS4ML or similar tools
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- Machine learning frameworks (e.g. TensorFlow, PyTorch)
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- AI model optimisation for hardware (quantisation, pruning)
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- RTL and digital design basics
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- Arm-based SoC and accelerator integration concepts
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- Software–hardware co-design
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- Reproducible design workflows
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## Resources from Arm and our partners
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# TODO
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## Support Level
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This project is designed to be self-serve but comes with opportunity of some community support from Arm Ambassadors, who are part of the Arm Developer program. If you are not already part of our program, [click here to join](https://www.arm.com/resources/developer-program?#register).
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This project can also be supported by SoC Labs in Southampton.
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# TODO
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## Benefits
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Standout project contributions will result in digital badges for CV building, recognised by Arm Talent Acquisition. We are currently discussing with national agencies the potential for funding streams for Arm Developer Labs projects, which would flow to you, not us.
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To receive the benefits, you must show us your project through our [online form](https://forms.office.com/e/VZnJQLeRhD). Please do not include any confidential information in your contribution. Additionally if you are affiliated with an academic institution, please ensure you have the right to share your material.
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‎docs/Challenge_Page.html‎

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</ul>
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</div>
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</details>
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<details class="ch-accordion">
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<summary>
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<span class="ch-acc-title">Q11: Can the participants participate in this challenge by applying for more than 1 more problem statement?</span>
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</summary>
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<div class="ch-acc-body">
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<p>No, the participants can apply for only 1 problem statement out of the given 5 problem statements in this challenge.</p>
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</div>
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</details>
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</div>
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</div>

‎docs/_posts/2026-01-16-HLS4ML-AI-SoC_Design.md‎

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---
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title: HLS4ML - AI SoC Design
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description: Explore using HLS4ML, an open-source project developed at organisations including CERN, Fermilab, and MIT, to create hardware for AI, compatible with Arm IP to form an SoC capable of tape-out.
4+
subjects:
5+
- ML
6+
- Performance and Architecture
7+
requires-team:
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- No
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platform:
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- AI
11+
sw-hw:
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- Software
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- Hardware
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support-level:
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- Self-Service
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- Arm Ambassador Support
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publication-date: 2026-01-16
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license:
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status:
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- Hidden
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layout: article
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sidebar:
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nav: projects
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full_description: |-
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<img class="image image--xl" src="/Arm-Developer-Labs/images/Learn_on_Arm_banner.png" loading="lazy" decoding="async" />
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# SoC Labs Logo
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## Description
30+
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### Why is this important?
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Tools such as HLS4ML have proven extremely successful for rapid FPGA-based AI acceleration, particularly in research and edge-AI contexts. However, there is currently a significant gap between FPGA-targeted HLS workflows and reproducible, tape-out-ready ASIC design flows.
34+
35+
Many AI accelerator projects focus on a single model, dataset, or hardware target. This project instead focuses on defining a repeatable and auditable methodology for translating AI models into hardware IP suitable for integration into an Arm-based SoC and potential fabrication.
36+
37+
We are looking for a clear, well-documented path from AI model → HLS → RTL → Arm-based SoC → tape-out. This reduces the cost, risk, and expertise barrier for startups, academics, and independent developers to innovate on silicon.
38+
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### Project Summary
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This project explores the use of HLS4ML (and comparable HLS-based AI tools) to develop a repeatable, tape-out-capable workflow for creating AI accelerator IP that can be integrated with Arm IP into a full SoC design.
42+
43+
The focus is not on a single accelerator or model, but on defining a methodology that includes:
44+
45+
AI and software layer
46+
- Selection of AI models (e.g. CNNs, transformers, or classical ML models).
47+
- Quantisation, pruning, and model optimisation strategies compatible with hardware implementation.
48+
- Clear mapping between software frameworks (e.g. TensorFlow / PyTorch) and hardware-friendly representations.
49+
50+
Hardware generation layer
51+
- Use of HLS4ML (or alternatives where appropriate) to generate synthesizable RTL.
52+
- Identification of constraints and modifications required to move from FPGA-oriented HLS outputs to ASIC-suitable RTL.
53+
- Definition of design rules, interfaces, and verification steps that ensure reproducibility.
54+
55+
SoC Design
56+
- Integration of the generated accelerator as an IP block within an Arm-based SoC.
57+
- Documentation of the additional steps required beyond FPGA validation: synthesis targets, timing closure considerations, verification, and power/area trade-offs.
58+
- Clear identification of what changes are needed to move from “works on FPGA” to “ready for fabrication”.
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60+
The output of this project is a reference flow, example designs, and documentation that others can follow to reproducibly generate AI accelerator IP suitable for integration into real Arm-based silicon.
61+
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## What will you use?
63+
You should be familiar with, or willing to learn about:
64+
- High-level Synthesis (HLS), including HLS4ML or similar tools
65+
- Machine learning frameworks (e.g. TensorFlow, PyTorch)
66+
- AI model optimisation for hardware (quantisation, pruning)
67+
- RTL and digital design basics
68+
- Arm-based SoC and accelerator integration concepts
69+
- Software–hardware co-design
70+
- Reproducible design workflows
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## Resources from Arm and our partners
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# TODO
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## Support Level
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This project is designed to be self-serve but comes with opportunity of some community support from Arm Ambassadors, who are part of the Arm Developer program. If you are not already part of our program, [click here to join](https://www.arm.com/resources/developer-program?#register).
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This project can also be supported by SoC Labs in Southampton.
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# TODO
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## Benefits
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Standout project contributions will result in digital badges for CV building, recognised by Arm Talent Acquisition. We are currently discussing with national agencies the potential for funding streams for Arm Developer Labs projects, which would flow to you, not us.
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To receive the benefits, you must show us your project through our [online form](https://forms.office.com/e/VZnJQLeRhD). Please do not include any confidential information in your contribution. Additionally if you are affiliated with an academic institution, please ensure you have the right to share your material.
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---
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<img class="image image--xl" src="/Arm-Developer-Labs/images/Learn_on_Arm_banner.png" loading="lazy" decoding="async" />
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# SoC Labs Logo
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## Description
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97+
### Why is this important?
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99+
Tools such as HLS4ML have proven extremely successful for rapid FPGA-based AI acceleration, particularly in research and edge-AI contexts. However, there is currently a significant gap between FPGA-targeted HLS workflows and reproducible, tape-out-ready ASIC design flows.
100+
101+
Many AI accelerator projects focus on a single model, dataset, or hardware target. This project instead focuses on defining a repeatable and auditable methodology for translating AI models into hardware IP suitable for integration into an Arm-based SoC and potential fabrication.
102+
103+
We are looking for a clear, well-documented path from AI model → HLS → RTL → Arm-based SoC → tape-out. This reduces the cost, risk, and expertise barrier for startups, academics, and independent developers to innovate on silicon.
104+
105+
### Project Summary
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This project explores the use of HLS4ML (and comparable HLS-based AI tools) to develop a repeatable, tape-out-capable workflow for creating AI accelerator IP that can be integrated with Arm IP into a full SoC design.
108+
109+
The focus is not on a single accelerator or model, but on defining a methodology that includes:
110+
111+
AI and software layer
112+
- Selection of AI models (e.g. CNNs, transformers, or classical ML models).
113+
- Quantisation, pruning, and model optimisation strategies compatible with hardware implementation.
114+
- Clear mapping between software frameworks (e.g. TensorFlow / PyTorch) and hardware-friendly representations.
115+
116+
Hardware generation layer
117+
- Use of HLS4ML (or alternatives where appropriate) to generate synthesizable RTL.
118+
- Identification of constraints and modifications required to move from FPGA-oriented HLS outputs to ASIC-suitable RTL.
119+
- Definition of design rules, interfaces, and verification steps that ensure reproducibility.
120+
121+
SoC Design
122+
- Integration of the generated accelerator as an IP block within an Arm-based SoC.
123+
- Documentation of the additional steps required beyond FPGA validation: synthesis targets, timing closure considerations, verification, and power/area trade-offs.
124+
- Clear identification of what changes are needed to move from “works on FPGA” to “ready for fabrication”.
125+
126+
The output of this project is a reference flow, example designs, and documentation that others can follow to reproducibly generate AI accelerator IP suitable for integration into real Arm-based silicon.
127+
128+
## What will you use?
129+
You should be familiar with, or willing to learn about:
130+
- High-level Synthesis (HLS), including HLS4ML or similar tools
131+
- Machine learning frameworks (e.g. TensorFlow, PyTorch)
132+
- AI model optimisation for hardware (quantisation, pruning)
133+
- RTL and digital design basics
134+
- Arm-based SoC and accelerator integration concepts
135+
- Software–hardware co-design
136+
- Reproducible design workflows
137+
138+
## Resources from Arm and our partners
139+
140+
# TODO
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## Support Level
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144+
This project is designed to be self-serve but comes with opportunity of some community support from Arm Ambassadors, who are part of the Arm Developer program. If you are not already part of our program, [click here to join](https://www.arm.com/resources/developer-program?#register).
145+
146+
This project can also be supported by SoC Labs in Southampton.
147+
# TODO
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## Benefits
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151+
Standout project contributions will result in digital badges for CV building, recognised by Arm Talent Acquisition. We are currently discussing with national agencies the potential for funding streams for Arm Developer Labs projects, which would flow to you, not us.
152+
153+
154+
To receive the benefits, you must show us your project through our [online form](https://forms.office.com/e/VZnJQLeRhD). Please do not include any confidential information in your contribution. Additionally if you are affiliated with an academic institution, please ensure you have the right to share your material.

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