[Test] Add and update tests for lrint/llrint (NFC) (#152662)

Many backends are missing either all tests for lrint, or specifically
those for f16, which currently crashes for `softPromoteHalf` targets.
For a number of popular backends, do the following:

* Ensure f16, f32, f64, and f128 are all covered
* Ensure both a 32- and 64-bit target are tested, if relevant
* Add `nounwind` to clean up CFI output
* Add a test covering the above if one did not exist
* Always specify the integer type in intrinsic calls

There are quite a few FIXMEs here, especially for `f16`, but much of
this will be resolved in the near future.

Author: tgross35

llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll

@@ -1,13 +1,23 @@
 ; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft | FileCheck %s --check-prefix=SOFTFP
 ; RUN: llc < %s -mtriple=arm-eabi -float-abi=hard | FileCheck %s --check-prefix=HARDFP
 
+; SOFTFP-LABEL: testmsxh_builtin:
+; SOFTFP:       bl      llrintf
+; HARDFP-LABEL: testmsxh_builtin:
+; HARDFP:       bl      llrintf
+define i64 @testmsxh_builtin(half %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
+  ret i64 %0
+}
+
 ; SOFTFP-LABEL: testmsxs_builtin:
 ; SOFTFP:       bl      llrintf
 ; HARDFP-LABEL: testmsxs_builtin:
 ; HARDFP:       bl      llrintf
 define i64 @testmsxs_builtin(float %x) {
 entry:
-  %0 = tail call i64 @llvm.llrint.f32(float %x)
+  %0 = tail call i64 @llvm.llrint.i64.f32(float %x)
   ret i64 %0
 }
 
@@ -17,9 +27,20 @@ entry:
 ; HARDFP:       bl      llrint
 define i64 @testmsxd_builtin(double %x) {
 entry:
-  %0 = tail call i64 @llvm.llrint.f64(double %x)
+  %0 = tail call i64 @llvm.llrint.i64.f64(double %x)
+  ret i64 %0
+}
+
+; FIXME(#44744): incorrect libcall
+; SOFTFP-LABEL: testmsxq_builtin:
+; SOFTFP:       bl      llrintl
+; HARDFP-LABEL: testmsxq_builtin:
+; HARDFP:       bl      llrintl
+define i64 @testmsxq_builtin(fp128 %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.i64.f128(fp128 %x)
   ret i64 %0
 }
 
-declare i64 @llvm.llrint.f32(float) nounwind readnone
-declare i64 @llvm.llrint.f64(double) nounwind readnone
+declare i64 @llvm.llrint.i64.f32(float) nounwind readnone
+declare i64 @llvm.llrint.i64.f64(double) nounwind readnone

llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll

@@ -1,6 +1,13 @@
 ; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft | FileCheck %s --check-prefix=SOFTFP
 ; RUN: llc < %s -mtriple=arm-eabi -float-abi=hard | FileCheck %s --check-prefix=HARDFP
 
+; FIXME: crash
+; define i32 @testmswh_builtin(half %x) {
+; entry:
+;   %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
+;   ret i32 %0
+; }
+
 ; SOFTFP-LABEL: testmsws_builtin:
 ; SOFTFP:       bl      lrintf
 ; HARDFP-LABEL: testmsws_builtin:
@@ -21,5 +28,16 @@ entry:
   ret i32 %0
 }
 
+; FIXME(#44744): incorrect libcall
+; SOFTFP-LABEL: testmswq_builtin:
+; SOFTFP:       bl      lrintl
+; HARDFP-LABEL: testmswq_builtin:
+; HARDFP:       bl      lrintl
+define i32 @testmswq_builtin(fp128 %x) {
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f128(fp128 %x)
+  ret i32 %0
+}
+
 declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
 declare i32 @llvm.lrint.i32.f64(double) nounwind readnone