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Automerge: [AArch64] Use DAG.getNegative instead of getNegatedInteger (NFC) (#157342)
2 parents 3fdac4a + 7bc342e commit 0c1727f

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llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 5 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -21060,13 +21060,6 @@ static bool isNegatedInteger(SDValue Op) {
2106021060
return Op.getOpcode() == ISD::SUB && isNullConstant(Op.getOperand(0));
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}
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21063-
static SDValue getNegatedInteger(SDValue Op, SelectionDAG &DAG) {
21064-
SDLoc DL(Op);
21065-
EVT VT = Op.getValueType();
21066-
SDValue Zero = DAG.getConstant(0, DL, VT);
21067-
return DAG.getNode(ISD::SUB, DL, VT, Zero, Op);
21068-
}
21069-
2107021063
// Try to fold
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//
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// (neg (csel X, Y)) -> (csel (neg X), (neg Y))
@@ -21085,16 +21078,17 @@ static SDValue performNegCSelCombine(SDNode *N, SelectionDAG &DAG) {
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SDValue N0 = CSel.getOperand(0);
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SDValue N1 = CSel.getOperand(1);
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21088-
// If both of them is not negations, it's not worth the folding as it
21081+
// If neither of them are negations, it's not worth the folding as it
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// introduces two additional negations while reducing one negation.
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if (!isNegatedInteger(N0) && !isNegatedInteger(N1))
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return SDValue();
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21093-
SDValue N0N = getNegatedInteger(N0, DAG);
21094-
SDValue N1N = getNegatedInteger(N1, DAG);
21095-
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SDLoc DL(N);
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EVT VT = CSel.getValueType();
21088+
21089+
SDValue N0N = DAG.getNegative(N0, DL, VT);
21090+
SDValue N1N = DAG.getNegative(N1, DL, VT);
21091+
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return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0N, N1N, CSel.getOperand(2),
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CSel.getOperand(3));
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}

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