[RISCV] Add X0_Pair to RISCVDeadRegisterDefinitions. (#141831)

Author: topperc

llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp

@@ -99,6 +99,8 @@ bool RISCVDeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
           X0Reg = RISCV::X0_W;
         } else if (RC && RC->contains(RISCV::X0_H)) {
           X0Reg = RISCV::X0_H;
+        } else if (RC && RC->contains(RISCV::X0_Pair)) {
+          X0Reg = RISCV::X0_Pair;
         } else {
           LLVM_DEBUG(dbgs() << "    Ignoring, register is not a GPR.\n");
           continue;

llvm/test/CodeGen/RISCV/double-mem.ll

@@ -141,10 +141,10 @@ define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
 ; RV32IZFINXZDINXZILSD:       # %bb.0:
 ; RV32IZFINXZDINXZILSD-NEXT:    lui a4, %hi(G)
 ; RV32IZFINXZDINXZILSD-NEXT:    fadd.d a0, a0, a2
-; RV32IZFINXZDINXZILSD-NEXT:    ld a2, %lo(G)(a4)
+; RV32IZFINXZDINXZILSD-NEXT:    ld zero, %lo(G)(a4)
 ; RV32IZFINXZDINXZILSD-NEXT:    addi a2, a4, %lo(G)
 ; RV32IZFINXZDINXZILSD-NEXT:    sd a0, %lo(G)(a4)
-; RV32IZFINXZDINXZILSD-NEXT:    ld a4, 72(a2)
+; RV32IZFINXZDINXZILSD-NEXT:    ld zero, 72(a2)
 ; RV32IZFINXZDINXZILSD-NEXT:    sd a0, 72(a2)
 ; RV32IZFINXZDINXZILSD-NEXT:    ret
 ; Use %a and %b in an FP op to ensure floating point registers are used, even

llvm/test/CodeGen/RISCV/zilsd.ll

@@ -8,7 +8,7 @@ define i64 @load(ptr %a) nounwind {
 ; CHECK-LABEL: load:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ld a2, 80(a0)
-; CHECK-NEXT:    ld a0, 0(a0)
+; CHECK-NEXT:    ld zero, 0(a0)
 ; CHECK-NEXT:    mv a0, a2
 ; CHECK-NEXT:    mv a1, a3
 ; CHECK-NEXT:    ret