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Automerge: [RISCV] Make MOP/HINT-based instruction mnemonics always available (#178609)
Per the psABI discussion in riscv-non-isa/riscv-elf-psabi-doc#474, the conclusion was to NOT introduce a new build attribute for MOP/HINT encoding reinterpretation. Instead, the toolchain should recognize these mnemonics unconditionally in the assembler and disassembler. The rationale is that these encodings occupy reserved hint/MOP space that is architecturally guaranteed not to trap on any compliant implementation. Requiring explicit extension flags creates unnecessary friction for users who simply want to write or read these instructions, while providing no real safety benefit since the encodings are always valid. Note: Ideally, the ISA specification would explicitly guarantee that these MOP/HINT encodings will never be reassigned to conflicting instructions. However, the ISA architects prefer to preserve flexibility in this area rather than making such guarantees in the spec. Given the practical reality that reassignment is highly unlikely, the toolchain takes the pragmatic approach of always recognizing these mnemonics. This change makes the following mnemonics always available: - lpad (Zicfilp): AUIPC hint encoding, always valid - pause (Zihintpause): FENCE hint encoding, always valid - ntl.* (Zihintntl): ADD hint encoding, always valid - c.ntl.* (Zihintntl+C): requires C extension only - sspush/sspopchk/ssrdp (Zicfiss): requires Zimop only (MOP encoding) - c.sspush/c.sspopchk (Zicfiss+Zcmop): requires Zcmop only Note: ssamoswap.w/d still requires Zicfiss as they use AMO encoding space rather than MOP encoding. Codegen patterns remain unchanged in this patch - generating these instructions in the compiler backend still requires the full extension to be enabled. A follow-up patch will relax this restriction as well, since these instructions are fundamentally MOP/HINT encodings that should be safe to generate regardless of extension availability. Link: riscv-non-isa/riscv-elf-psabi-doc#474
2 parents 1f66d51 + 466c22b commit 1975654

17 files changed

+162
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lines changed

‎llvm/docs/ReleaseNotes.md‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -125,6 +125,10 @@ Changes to the RISC-V Backend
125125
* `llvm-objdump` now has support for `--symbolize-operands` with RISC-V.
126126
* `-mcpu=spacemit-x100` was added.
127127
* Change P extension version to match the 019 draft specification. Encoded in `-march` as `0p19`.
128+
* Mnemonics for MOP/HINT-based instructions (`lpad`, `pause`, `ntl.*`, `c.ntl.*`,
129+
`sspush`, `sspopchk`, `ssrdp`, `c.sspush`, `c.sspopchk`) are now always
130+
available in the assembler and disassembler without requiring their respective
131+
extensions.
128132

129133
Changes to the WebAssembly Backend
130134
----------------------------------

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td‎

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1115,7 +1115,8 @@ def : InstAlias<"jalr $rd, (${rs})", (JALR GPR:$rd, GPR:$rs, 0), 0>;
11151115

11161116
def : InstAlias<"fence", (FENCE 0xF, 0xF)>; // 0xF == iorw
11171117

1118-
let Predicates = [HasStdExtZihintpause] in
1118+
// pause is always available in the assembler and disassembler, even without
1119+
// enabling Zihintpause, per psABI decision (riscv-non-isa/riscv-elf-psabi-doc#474).
11191120
def : InstAlias<"pause", (FENCE 0x1, 0x0)>; // 0x1 == w
11201121

11211122
def : InstAlias<"rdinstret $rd", (CSRRS GPR:$rd, INSTRET.Encoding, X0), 2>;
@@ -1156,12 +1157,13 @@ def : InstAlias<"hfence.gvma $rs", (HFENCE_GVMA GPR:$rs, X0)>;
11561157
def : InstAlias<"hfence.vvma", (HFENCE_VVMA X0, X0), 2>;
11571158
def : InstAlias<"hfence.vvma $rs", (HFENCE_VVMA GPR:$rs, X0)>;
11581159

1159-
let Predicates = [HasStdExtZihintntl] in {
1160-
def : InstAlias<"ntl.p1", (ADD X0, X0, X2)>;
1161-
def : InstAlias<"ntl.pall", (ADD X0, X0, X3)>;
1162-
def : InstAlias<"ntl.s1", (ADD X0, X0, X4)>;
1163-
def : InstAlias<"ntl.all", (ADD X0, X0, X5)>;
1164-
} // Predicates = [HasStdExtZihintntl]
1160+
// ntl.* hints are always available in the assembler and disassembler, even
1161+
// without enabling Zihintntl, per psABI decision
1162+
// (riscv-non-isa/riscv-elf-psabi-doc#474).
1163+
def : InstAlias<"ntl.p1", (ADD X0, X0, X2)>;
1164+
def : InstAlias<"ntl.pall", (ADD X0, X0, X3)>;
1165+
def : InstAlias<"ntl.s1", (ADD X0, X0, X4)>;
1166+
def : InstAlias<"ntl.all", (ADD X0, X0, X5)>;
11651167

11661168
let EmitPriority = 0 in {
11671169
def : InstAlias<"lb $rd, (${rs1})",
@@ -1229,9 +1231,9 @@ def : MnemonicAlias<"sbreak", "ebreak">;
12291231

12301232
def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>;
12311233

1232-
let Predicates = [HasStdExtZicfilp] in {
1234+
// lpad is always available in the assembler and disassembler, even without
1235+
// enabling Zicfilp, per psABI decision (riscv-non-isa/riscv-elf-psabi-doc#474).
12331236
def : InstAlias<"lpad $imm20", (AUIPC X0, uimm20:$imm20)>;
1234-
}
12351237

12361238
//===----------------------------------------------------------------------===//
12371239
// .insn directive instructions

‎llvm/lib/Target/RISCV/RISCVInstrInfoC.td‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -596,12 +596,14 @@ def : InstAlias<"c.srli64 $rs1", (C_SRLI GPRC:$rs1, 0), 0>;
596596
def : InstAlias<"c.srai64 $rs1", (C_SRAI GPRC:$rs1, 0), 0>;
597597
}
598598

599-
let Predicates = [HasStdExtC, HasStdExtZihintntl] in {
599+
// c.ntl.* hints are always available when Zca is present, even without
600+
// enabling Zihintntl, per psABI decision (riscv-non-isa/riscv-elf-psabi-doc#474).
601+
let Predicates = [HasStdExtZca] in {
600602
def : InstAlias<"c.ntl.p1", (C_ADD X0, X2)>;
601603
def : InstAlias<"c.ntl.pall", (C_ADD X0, X3)>;
602604
def : InstAlias<"c.ntl.s1", (C_ADD X0, X4)>;
603605
def : InstAlias<"c.ntl.all", (C_ADD X0, X5)>;
604-
} // Predicates = [HasStdExtC, HasStdExtZihintntl]
606+
} // Predicates = [HasStdExtZca]
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606608
let EmitPriority = 0 in {
607609
let Predicates = [HasStdExtZca] in {

‎llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,9 @@ class CMOPInst<bits<3> imm3, string opcodestr>
2020
let Inst{12-11} = 0;
2121
}
2222

23-
foreach n = [1, 3, 5, 7, 9, 11, 13, 15] in {
23+
// c.mop.1 and c.mop.5 are aliases for c.sspush and c.sspopchk respectively,
24+
// defined in RISCVInstrInfoZicfiss.td.
25+
foreach n = [3, 7, 9, 11, 13, 15] in {
2426
let Predicates = [HasStdExtZcmop] in
2527
def C_MOP_ # n : CMOPInst<!srl(n, 1), "c.mop." # n>, Sched<[]>;
2628
}

‎llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td‎

Lines changed: 20 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,10 @@ class RVC_SSInst<bits<5> rs1val, RegisterClass reg_class, string opcodestr> :
2424
// Instructions
2525
//===----------------------------------------------------------------------===//
2626

27-
let Predicates = [HasStdExtZicfiss] in {
27+
// Zicfiss instructions that use Zimop encoding space are available when Zimop
28+
// is enabled, without requiring Zicfiss explicitly. Per psABI decision
29+
// (riscv-non-isa/riscv-elf-psabi-doc#474).
30+
let Predicates = [HasStdExtZimop] in {
2831
let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
2932
def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "sspopchk",
3033
"$rs1"> {
@@ -45,16 +48,19 @@ def SSPUSH : RVInstR<0b1100111, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2),
4548
let rd = 0b00000;
4649
let rs1 = 0b00000;
4750
}
48-
} // Predicates = [HasStdExtZicfiss]
51+
} // Predicates = [HasStdExtZimop]
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50-
let Predicates = [HasStdExtZicfiss, HasStdExtZcmop],
53+
// Compressed Zicfiss instructions use Zcmop encoding space and are available
54+
// when Zcmop is enabled, without requiring Zicfiss explicitly. Per psABI
55+
// decision (riscv-non-isa/riscv-elf-psabi-doc#474).
56+
let Predicates = [HasStdExtZcmop],
5157
DecoderNamespace = "Zicfiss" in {
5258
let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
5359
def C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.sspush">;
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5561
let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
5662
def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">;
57-
} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop]
63+
} // Predicates = [HasStdExtZcmop]
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5965
let Predicates = [HasStdExtZicfiss] in
6066
defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">;
@@ -74,14 +80,21 @@ def PseudoMOP_SSPOPCHK : Pseudo<(outs), (ins GPRX1X5:$rs1), []>,
7480
let Predicates = [HasStdExtZcmop] in {
7581
let Uses = [X1], hasSideEffects = 1, mayLoad = 0, mayStore = 1 in
7682
def PseudoMOP_C_SSPUSH : Pseudo<(outs), (ins), []>,
77-
PseudoInstExpansion<(C_MOP_1)>;
83+
PseudoInstExpansion<(C_SSPUSH X1)>;
7884
} // Predicates = [HasStdExtZcmop]
7985

8086
//===----------------------------------------------------------------------===/
8187
// Compress Instruction tablegen backend.
8288
//===----------------------------------------------------------------------===//
8389

84-
let Predicates = [HasStdExtZicfiss, HasStdExtZcmop] in {
90+
let Predicates = [HasStdExtZcmop] in {
8591
def : CompressPat<(SSPUSH X1), (C_SSPUSH X1)>;
8692
def : CompressPat<(SSPOPCHK X5), (C_SSPOPCHK X5)>;
87-
} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop]
93+
} // Predicates = [HasStdExtZcmop]
94+
95+
// c.mop.1 and c.mop.5 are aliases for c.sspush ra and c.sspopchk t0.
96+
// Use EmitPriority=0 so disassembler prints c.sspush/c.sspopchk.
97+
let Predicates = [HasStdExtZcmop], EmitPriority = 0 in {
98+
def : InstAlias<"c.mop.1", (C_SSPUSH X1)>;
99+
def : InstAlias<"c.mop.5", (C_SSPOPCHK X5)>;
100+
} // Predicates = [HasStdExtZcmop], EmitPriority = 0

‎llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -204,7 +204,7 @@
204204
0x7D 0x70
205205

206206
# BAD: invalid instruction encoding
207-
# MOP: c.mop.1
207+
# MOP: c.sspush ra
208208
0x81 0x60
209209

210210
# GOOD: c.lui ra, 1
@@ -782,7 +782,7 @@
782782
0x7D 0x72
783783

784784
# BAD: invalid instruction encoding
785-
# MOP: c.mop.5
785+
# MOP: c.sspopchk t0
786786
0x81 0x62
787787

788788
# GOOD: c.lui t0, 1

‎llvm/test/MC/RISCV/compressed-zicfiss.s‎

Lines changed: 22 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -9,45 +9,59 @@
99
# RUN: | llvm-objdump --mattr=+experimental-zicfiss,+zcmop -M no-aliases -d -r - \
1010
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
1111
#
12+
# Compressed Zicfiss instructions only require Zcmop (and Zimop for
13+
# uncompressed forms), not Zicfiss (riscv-non-isa/riscv-elf-psabi-doc#474).
14+
#
15+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zcmop,+zimop -M no-aliases -show-encoding \
16+
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
17+
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zcmop,+zimop < %s \
18+
# RUN: | llvm-objdump --mattr=+zcmop,+zimop -M no-aliases -d -r - \
19+
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
20+
# RUN: llvm-mc %s -triple=riscv64 -mattr=+zcmop,+zimop -M no-aliases -show-encoding \
21+
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
22+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zcmop,+zimop < %s \
23+
# RUN: | llvm-objdump --mattr=+zcmop,+zimop -M no-aliases -d -r - \
24+
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
25+
#
1226
# RUN: not llvm-mc -triple riscv32 -M no-aliases -show-encoding < %s 2>&1 \
1327
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
1428

1529
# CHECK-ASM-AND-OBJ: c.sspopchk t0
1630
# CHECK-ASM: encoding: [0x81,0x62]
17-
# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
31+
# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations)
1832
sspopchk x5
1933

2034
# CHECK-ASM-AND-OBJ: c.sspopchk t0
2135
# CHECK-ASM: encoding: [0x81,0x62]
22-
# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
36+
# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations)
2337
sspopchk t0
2438

2539
# CHECK-ASM-AND-OBJ: c.sspush ra
2640
# CHECK-ASM: encoding: [0x81,0x60]
27-
# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
41+
# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations)
2842
sspush x1
2943

3044
# CHECK-ASM-AND-OBJ: c.sspush ra
3145
# CHECK-ASM: encoding: [0x81,0x60]
32-
# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
46+
# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations)
3347
sspush ra
3448

3549
# CHECK-ASM-AND-OBJ: c.sspush ra
3650
# CHECK-ASM: encoding: [0x81,0x60]
37-
# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
51+
# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations)
3852
c.sspush x1
3953

4054
# CHECK-ASM-AND-OBJ: c.sspush ra
4155
# CHECK-ASM: encoding: [0x81,0x60]
42-
# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
56+
# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations)
4357
c.sspush ra
4458

4559
# CHECK-ASM-AND-OBJ: c.sspopchk t0
4660
# CHECK-ASM: encoding: [0x81,0x62]
47-
# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
61+
# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations)
4862
c.sspopchk x5
4963

5064
# CHECK-ASM-AND-OBJ: c.sspopchk t0
5165
# CHECK-ASM: encoding: [0x81,0x62]
52-
# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
66+
# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations)
5367
c.sspopchk t0

‎llvm/test/MC/RISCV/invalid-instruction-spellcheck.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@
1111
# which are valid for the current set of features
1212

1313
ad x1, x1, x1
14-
# CHECK-RV32: did you mean: add, addi, and, andi, la
15-
# CHECK-RV64: did you mean: add, addi, addw, and, andi, la, ld, sd
14+
# CHECK-RV32: did you mean: add, addi, and, andi, la, lpad
15+
# CHECK-RV64: did you mean: add, addi, addw, and, andi, la, ld, lpad, sd
1616
# CHECK-NEXT: ad x1, x1, x1
1717

1818
fl ft0, 0(sp)

‎llvm/test/MC/RISCV/rv32i-invalid.s‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -196,7 +196,6 @@ sh1add a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the followi
196196
clz a0, a1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation){{$}}
197197
clmul a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography){{$}}
198198
bset a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbs' (Single-Bit Instructions){{$}}
199-
pause # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zihintpause' (Pause Hint){{$}}
200199

201200
# Using floating point registers when integer registers are expected
202201
addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction

‎llvm/test/MC/RISCV/rvzcmop-valid.s‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,15 +9,17 @@
99
# RUN: | llvm-objdump --mattr=+zcmop -d -r - \
1010
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
1111

12-
# CHECK-ASM-AND-OBJ: c.mop.1
12+
# c.mop.1 is an alias for c.sspush ra.
13+
# CHECK-ASM-AND-OBJ: c.sspush ra
1314
# CHECK-ASM: encoding: [0x81,0x60]
1415
c.mop.1
1516

1617
# CHECK-ASM-AND-OBJ: c.mop.3
1718
# CHECK-ASM: encoding: [0x81,0x61]
1819
c.mop.3
1920

20-
# CHECK-ASM-AND-OBJ: c.mop.5
21+
# c.mop.5 is an alias for c.sspopchk t0.
22+
# CHECK-ASM-AND-OBJ: c.sspopchk t0
2123
# CHECK-ASM: encoding: [0x81,0x62]
2224
c.mop.5
2325

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