@@ -860,7 +860,7 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
860860 .addUse (GV);
861861 return MIB.constrainAllUses (TII, TRI, RBI) &&
862862 BuildMI (BB, I, I.getDebugLoc (),
863- TII.get (STI.isVulkanEnv ()
863+ TII.get (STI.isLogicalSPIRV ()
864864 ? SPIRV::OpInBoundsAccessChain
865865 : SPIRV::OpInBoundsPtrAccessChain))
866866 .addDef (ResVReg)
@@ -1034,7 +1034,7 @@ bool SPIRVInstructionSelector::selectUnOp(Register ResVReg,
10341034 const SPIRVType *ResType,
10351035 MachineInstr &I,
10361036 unsigned Opcode) const {
1037- if (STI.isOpenCLEnv () && I.getOperand (1 ).isReg ()) {
1037+ if (STI.isPhysicalSPIRV () && I.getOperand (1 ).isReg ()) {
10381038 Register SrcReg = I.getOperand (1 ).getReg ();
10391039 bool IsGV = false ;
10401040 for (MachineRegisterInfo::def_instr_iterator DefIt =
@@ -2062,7 +2062,7 @@ bool SPIRVInstructionSelector::selectDot4AddPackedExpansion(
20622062 auto ExtractOp =
20632063 Signed ? SPIRV::OpBitFieldSExtract : SPIRV::OpBitFieldUExtract;
20642064
2065- bool ZeroAsNull = STI.isOpenCLEnv ();
2065+ bool ZeroAsNull = ! STI.isShader ();
20662066 // Extract the i8 element, multiply and add it to the accumulator
20672067 for (unsigned i = 0 ; i < 4 ; i++) {
20682068 // A[i]
@@ -2202,7 +2202,7 @@ bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg,
22022202 .addDef (ResVReg)
22032203 .addUse (GR.getSPIRVTypeID (ResType))
22042204 .addUse (GR.getOrCreateConstInt (SPIRV::Scope::Subgroup, I,
2205- IntTy, TII, STI.isOpenCLEnv ()));
2205+ IntTy, TII, ! STI.isShader ()));
22062206
22072207 for (unsigned J = 2 ; J < I.getNumOperands (); J++) {
22082208 BMI.addUse (I.getOperand (J).getReg ());
@@ -2226,7 +2226,7 @@ bool SPIRVInstructionSelector::selectWaveActiveCountBits(
22262226 .addDef (ResVReg)
22272227 .addUse (GR.getSPIRVTypeID (ResType))
22282228 .addUse (GR.getOrCreateConstInt (SPIRV::Scope::Subgroup, I, IntTy,
2229- TII, STI.isOpenCLEnv ()))
2229+ TII, ! STI.isShader ()))
22302230 .addImm (SPIRV::GroupOperation::Reduce)
22312231 .addUse (BallotReg)
22322232 .constrainAllUses (TII, TRI, RBI);
@@ -2257,7 +2257,7 @@ bool SPIRVInstructionSelector::selectWaveReduceMax(Register ResVReg,
22572257 .addDef (ResVReg)
22582258 .addUse (GR.getSPIRVTypeID (ResType))
22592259 .addUse (GR.getOrCreateConstInt (SPIRV::Scope::Subgroup, I, IntTy, TII,
2260- STI.isOpenCLEnv ()))
2260+ ! STI.isShader ()))
22612261 .addImm (SPIRV::GroupOperation::Reduce)
22622262 .addUse (I.getOperand (2 ).getReg ())
22632263 .constrainAllUses (TII, TRI, RBI);
@@ -2284,7 +2284,7 @@ bool SPIRVInstructionSelector::selectWaveReduceSum(Register ResVReg,
22842284 .addDef (ResVReg)
22852285 .addUse (GR.getSPIRVTypeID (ResType))
22862286 .addUse (GR.getOrCreateConstInt (SPIRV::Scope::Subgroup, I, IntTy, TII,
2287- STI.isOpenCLEnv ()))
2287+ ! STI.isShader ()))
22882288 .addImm (SPIRV::GroupOperation::Reduce)
22892289 .addUse (I.getOperand (2 ).getReg ());
22902290}
@@ -2506,7 +2506,7 @@ bool SPIRVInstructionSelector::selectFCmp(Register ResVReg,
25062506Register SPIRVInstructionSelector::buildZerosVal (const SPIRVType *ResType,
25072507 MachineInstr &I) const {
25082508 // OpenCL uses nulls for Zero. In HLSL we don't use null constants.
2509- bool ZeroAsNull = STI.isOpenCLEnv ();
2509+ bool ZeroAsNull = ! STI.isShader ();
25102510 if (ResType->getOpcode () == SPIRV::OpTypeVector)
25112511 return GR.getOrCreateConstVector (0UL , I, ResType, TII, ZeroAsNull);
25122512 return GR.getOrCreateConstInt (0 , I, ResType, TII, ZeroAsNull);
@@ -2515,7 +2515,7 @@ Register SPIRVInstructionSelector::buildZerosVal(const SPIRVType *ResType,
25152515Register SPIRVInstructionSelector::buildZerosValF (const SPIRVType *ResType,
25162516 MachineInstr &I) const {
25172517 // OpenCL uses nulls for Zero. In HLSL we don't use null constants.
2518- bool ZeroAsNull = STI.isOpenCLEnv ();
2518+ bool ZeroAsNull = ! STI.isShader ();
25192519 APFloat VZero = getZeroFP (GR.getTypeForSPIRVType (ResType));
25202520 if (ResType->getOpcode () == SPIRV::OpTypeVector)
25212521 return GR.getOrCreateConstVector (VZero, I, ResType, TII, ZeroAsNull);
@@ -2525,7 +2525,7 @@ Register SPIRVInstructionSelector::buildZerosValF(const SPIRVType *ResType,
25252525Register SPIRVInstructionSelector::buildOnesValF (const SPIRVType *ResType,
25262526 MachineInstr &I) const {
25272527 // OpenCL uses nulls for Zero. In HLSL we don't use null constants.
2528- bool ZeroAsNull = STI.isOpenCLEnv ();
2528+ bool ZeroAsNull = ! STI.isShader ();
25292529 APFloat VOne = getOneFP (GR.getTypeForSPIRVType (ResType));
25302530 if (ResType->getOpcode () == SPIRV::OpTypeVector)
25312531 return GR.getOrCreateConstVector (VOne, I, ResType, TII, ZeroAsNull);
@@ -2713,10 +2713,10 @@ bool SPIRVInstructionSelector::selectConst(Register ResVReg,
27132713 Reg = GR.getOrCreateConstNullPtr (MIRBuilder, ResType);
27142714 } else if (Opcode == TargetOpcode::G_FCONSTANT) {
27152715 Reg = GR.getOrCreateConstFP (I.getOperand (1 ).getFPImm ()->getValue (), I,
2716- ResType, TII, STI.isOpenCLEnv ());
2716+ ResType, TII, ! STI.isShader ());
27172717 } else {
27182718 Reg = GR.getOrCreateConstInt (I.getOperand (1 ).getCImm ()->getZExtValue (), I,
2719- ResType, TII, STI.isOpenCLEnv ());
2719+ ResType, TII, ! STI.isShader ());
27202720 }
27212721 return Reg == ResVReg ? true : BuildCOPY (ResVReg, Reg, I);
27222722}
@@ -2796,7 +2796,7 @@ bool SPIRVInstructionSelector::selectGEP(Register ResVReg,
27962796 // OpAccessChain could be used for OpenCL, but the SPIRV-LLVM Translator only
27972797 // relies on PtrAccessChain, so we'll try not to deviate. For Vulkan however,
27982798 // we have to use Op[InBounds]AccessChain.
2799- const unsigned Opcode = STI.isVulkanEnv ()
2799+ const unsigned Opcode = STI.isLogicalSPIRV ()
28002800 ? (IsGEPInBounds ? SPIRV::OpInBoundsAccessChain
28012801 : SPIRV::OpAccessChain)
28022802 : (IsGEPInBounds ? SPIRV::OpInBoundsPtrAccessChain
@@ -3493,7 +3493,7 @@ bool SPIRVInstructionSelector::selectFirstBitSet64Overflow(
34933493
34943494 // On odd component counts we need to handle one more component
34953495 if (CurrentComponent != ComponentCount) {
3496- bool ZeroAsNull = STI.isOpenCLEnv ();
3496+ bool ZeroAsNull = ! STI.isShader ();
34973497 Register FinalElemReg = MRI->createVirtualRegister (GR.getRegClass (I64Type));
34983498 Register ConstIntLastIdx = GR.getOrCreateConstInt (
34993499 ComponentCount - 1 , I, BaseType, TII, ZeroAsNull);
@@ -3523,7 +3523,7 @@ bool SPIRVInstructionSelector::selectFirstBitSet64(
35233523 Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
35243524 unsigned ComponentCount = GR.getScalarOrVectorComponentCount (ResType);
35253525 SPIRVType *BaseType = GR.retrieveScalarOrVectorIntType (ResType);
3526- bool ZeroAsNull = STI.isOpenCLEnv ();
3526+ bool ZeroAsNull = ! STI.isShader ();
35273527 Register ConstIntZero =
35283528 GR.getOrCreateConstInt (0 , I, BaseType, TII, ZeroAsNull);
35293529 Register ConstIntOne =
@@ -3725,7 +3725,7 @@ bool SPIRVInstructionSelector::selectAllocaArray(Register ResVReg,
37253725 .addUse (GR.getSPIRVTypeID (ResType))
37263726 .addUse (I.getOperand (2 ).getReg ())
37273727 .constrainAllUses (TII, TRI, RBI);
3728- if (!STI.isVulkanEnv ()) {
3728+ if (!STI.isShader ()) {
37293729 unsigned Alignment = I.getOperand (3 ).getImm ();
37303730 buildOpDecorate (ResVReg, I, TII, SPIRV::Decoration::Alignment, {Alignment});
37313731 }
@@ -3744,7 +3744,7 @@ bool SPIRVInstructionSelector::selectFrameIndex(Register ResVReg,
37443744 .addUse (GR.getSPIRVTypeID (ResType))
37453745 .addImm (static_cast <uint32_t >(SPIRV::StorageClass::Function))
37463746 .constrainAllUses (TII, TRI, RBI);
3747- if (!STI.isVulkanEnv ()) {
3747+ if (!STI.isShader ()) {
37483748 unsigned Alignment = I.getOperand (2 ).getImm ();
37493749 buildOpDecorate (ResVReg, *It, TII, SPIRV::Decoration::Alignment,
37503750 {Alignment});
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