@@ -121,29 +121,10 @@ static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
121121 return std::make_unique<ARMElfTargetObjectFile>();
122122}
123123
124- static ARMBaseTargetMachine::ARMABI
125- computeTargetABI (const Triple &TT, StringRef CPU,
126- const TargetOptions &Options) {
127- StringRef ABIName = Options.MCOptions .getABIName ();
128-
129- if (ABIName.empty ())
130- ABIName = ARM::computeDefaultTargetABI (TT, CPU);
131-
132- if (ABIName == " aapcs16" )
133- return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
134- else if (ABIName.starts_with (" aapcs" ))
135- return ARMBaseTargetMachine::ARM_ABI_AAPCS;
136- else if (ABIName.starts_with (" apcs" ))
137- return ARMBaseTargetMachine::ARM_ABI_APCS;
138-
139- llvm_unreachable (" Unhandled/unknown ABI Name!" );
140- return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
141- }
142-
143124static std::string computeDataLayout (const Triple &TT, StringRef CPU,
144125 const TargetOptions &Options,
145126 bool isLittle) {
146- auto ABI = computeTargetABI (TT, CPU, Options);
127+ auto ABI = ARM:: computeTargetABI (TT, CPU, Options. MCOptions . ABIName );
147128 std::string Ret;
148129
149130 if (isLittle)
@@ -163,19 +144,19 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
163144 Ret += " -Fi8" ;
164145
165146 // ABIs other than APCS have 64 bit integers with natural alignment.
166- if (ABI != ARMBaseTargetMachine ::ARM_ABI_APCS)
147+ if (ABI != ARM ::ARM_ABI_APCS)
167148 Ret += " -i64:64" ;
168149
169150 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
170151 // bits, others to 64 bits. We always try to align to 64 bits.
171- if (ABI == ARMBaseTargetMachine ::ARM_ABI_APCS)
152+ if (ABI == ARM ::ARM_ABI_APCS)
172153 Ret += " -f64:32:64" ;
173154
174155 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
175156 // to 64. We always ty to give them natural alignment.
176- if (ABI == ARMBaseTargetMachine ::ARM_ABI_APCS)
157+ if (ABI == ARM ::ARM_ABI_APCS)
177158 Ret += " -v64:32:64-v128:32:128" ;
178- else if (ABI != ARMBaseTargetMachine ::ARM_ABI_AAPCS16)
159+ else if (ABI != ARM ::ARM_ABI_AAPCS16)
179160 Ret += " -v128:64:128" ;
180161
181162 // Try to align aggregates to 32 bits (the default is 64 bits, which has no
@@ -187,9 +168,9 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
187168
188169 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
189170 // aligned everywhere else.
190- if (TT.isOSNaCl () || ABI == ARMBaseTargetMachine ::ARM_ABI_AAPCS16)
171+ if (TT.isOSNaCl () || ABI == ARM ::ARM_ABI_AAPCS16)
191172 Ret += " -S128" ;
192- else if (ABI == ARMBaseTargetMachine ::ARM_ABI_AAPCS)
173+ else if (ABI == ARM ::ARM_ABI_AAPCS)
193174 Ret += " -S64" ;
194175 else
195176 Ret += " -S32" ;
@@ -226,7 +207,7 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
226207 TT, CPU, FS, Options,
227208 getEffectiveRelocModel(TT, RM),
228209 getEffectiveCodeModel(CM, CodeModel::Small), OL),
229- TargetABI(computeTargetABI(TT, CPU, Options)),
210+ TargetABI(ARM:: computeTargetABI(TT, CPU, Options.MCOptions.ABIName )),
230211 TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
231212
232213 // Default to triple-appropriate float ABI
@@ -271,22 +252,6 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
271252
272253ARMBaseTargetMachine::~ARMBaseTargetMachine () = default ;
273254
274- bool ARMBaseTargetMachine::isAPCS_ABI () const {
275- assert (TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
276- return TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
277- }
278-
279- bool ARMBaseTargetMachine::isAAPCS_ABI () const {
280- assert (TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
281- return TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
282- TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
283- }
284-
285- bool ARMBaseTargetMachine::isAAPCS16_ABI () const {
286- assert (TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
287- return TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
288- }
289-
290255MachineFunctionInfo *ARMBaseTargetMachine::createMachineFunctionInfo (
291256 BumpPtrAllocator &Allocator, const Function &F,
292257 const TargetSubtargetInfo *STI) const {
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