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1 parent b92979a commit 523b4b0Copy full SHA for 523b4b0
clang/docs/ShadowCallStack.rst
@@ -61,7 +61,7 @@ The instrumentation makes use of the platform register ``x18`` on AArch64,
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``x3`` (``gp``) on RISC-V with software shadow stack and ``ssp`` on RISC-V with
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hardware shadow stack, which needs `Zicfiss`_ and ``-fcf-protection=return``.
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Users can choose between the software and hardware based shadow stack
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-implementation on RISC-V backend by passing ``-fsanitize=shadowcallstack``
+implementation on RISC-V backend by passing ``-fsanitize=shadow-call-stack``
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or ``Zicfiss`` with ``-fcf-protection=return``.
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For simplicity we will refer to this as the ``SCSReg``. On some platforms,
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``SCSReg`` is reserved, and on others, it is designated as a scratch register.
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