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[RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706)
This extension adds eight 48 bit large arithmetic instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support.
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‎clang/test/Driver/print-supported-extensions-riscv.c

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@@ -200,6 +200,7 @@
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// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
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// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
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// CHECK-NEXT: xqciint 0.2 'Xqciint' (Qualcomm uC Interrupts Extension)
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// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
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// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
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// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
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// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)

‎llvm/docs/RISCVUsage.rst

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@@ -450,6 +450,9 @@ The current vendor extensions supported are:
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``experimental-Xqciint``
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LLVM implements `version 0.2 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcilia``
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LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcilo``
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LLVM implements `version 0.2 of the Qualcomm uC Large Offset Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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‎llvm/docs/ReleaseNotes.md

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@@ -107,6 +107,9 @@ Changes to the PowerPC Backend
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Changes to the RISC-V Backend
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-----------------------------
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* Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large Immediate Arithmetic)
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extension.
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Changes to the WebAssembly Backend
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----------------------------------
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‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

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@@ -1056,6 +1056,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
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isInt<26>(fixImmediateForRV32(Imm, isRV64Imm()));
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}
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bool isSImm32() const {
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int64_t Imm;
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RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
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if (!isImm())
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return false;
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bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
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return IsConstantImm && isInt<32>(fixImmediateForRV32(Imm, isRV64Imm())) &&
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VK == RISCVMCExpr::VK_RISCV_None;
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}
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/// getStartLoc - Gets location of the first token of this operand
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SMLoc getStartLoc() const override { return StartLoc; }
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/// getEndLoc - Gets location of the last token of this operand
@@ -1665,6 +1675,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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case Match_InvalidSImm26:
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return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 25),
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(1 << 25) - 1);
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case Match_InvalidSImm32:
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return generateImmOutOfRangeError(Operands, ErrorInfo,
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std::numeric_limits<int32_t>::min(),
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std::numeric_limits<uint32_t>::max());
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case Match_InvalidRnumArg: {
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return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
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}

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

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@@ -767,6 +767,8 @@ DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
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for (size_t i = Size; i-- != 0;) {
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Insn += (static_cast<uint64_t>(Bytes[i]) << 8 * i);
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}
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcilia, DecoderTableXqcilia48,
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"Qualcomm uC Large Immediate Arithmetic 48bit");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcilo, DecoderTableXqcilo48,
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"Qualcomm uC Large Offset Load Store 48bit");
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‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

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@@ -327,6 +327,7 @@ enum OperandType : unsigned {
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OPERAND_SIMM12,
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OPERAND_SIMM12_LSB00000,
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OPERAND_SIMM26,
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OPERAND_SIMM32,
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OPERAND_CLUI_IMM,
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OPERAND_VTYPEI10,
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OPERAND_VTYPEI11,

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -1358,6 +1358,14 @@ def HasVendorXqciint
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AssemblerPredicate<(all_of FeatureVendorXqciint),
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"'Xqciint' (Qualcomm uC Interrupts Extension)">;
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def FeatureVendorXqcilia
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: RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Immediate Arithmetic Extension",
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[FeatureStdExtZca]>;
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def HasVendorXqcilia
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: Predicate<"Subtarget->hasVendorXqcilia()">,
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AssemblerPredicate<(all_of FeatureVendorXqcilia),
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"'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)">;
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def FeatureVendorXqcilo
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: RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Offset Load Store Extension",
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[FeatureStdExtZca]>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

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@@ -34,6 +34,21 @@ def uimm11 : RISCVUImmLeafOp<11>;
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def simm26 : RISCVSImmLeafOp<26>;
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// 32-bit Immediate, used by RV32 Instructions in 32-bit operations, so no
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// sign-/zero-extension. This is represented internally as a signed 32-bit value.
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def simm32 : RISCVOp<XLenVT> {
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let ParserMatchClass = SImmAsmOperand<32, "">;
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let EncoderMethod = "getImmOpValue";
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let DecoderMethod = "decodeSImmOperand<32>";
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let OperandType = "OPERAND_SIMM32";
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let MCOperandPredicate = [{
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int64_t Imm;
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if (MCOp.evaluateAsConstantImm(Imm))
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return isInt<32>(Imm);
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return false;
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}];
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}
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//===----------------------------------------------------------------------===//
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// Instruction Formats
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//===----------------------------------------------------------------------===//
@@ -245,6 +260,25 @@ class QCIRVInstESStore<bits<3> funct3, bits<2> funct2, string opcodestr>
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(ins GPRMem:$rs2, GPR:$rs1, simm26:$imm),
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opcodestr, "$rs2, ${imm}(${rs1})">;
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class QCIRVInstEAI<bits<3> funct3, bits<1> funct1, string opcodestr>
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: RVInst48<(outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, simm32:$imm),
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opcodestr, "$rd, $imm", [], InstFormatOther> {
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bits<5> rd;
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bits<32> imm;
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let Constraints = "$rd = $rd_wb";
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let Inst{47-16} = imm{31-0};
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let Inst{15} = funct1;
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let Inst{14-12} = funct3;
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let Inst{11-7} = rd;
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let Inst{6-0} = 0b0011111;
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}
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class QCIRVInstEI<bits<3> funct3, bits<2> funct2, string opcodestr>
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: QCIRVInstEIBase<funct3, funct2, (outs GPRNoX0:$rd),
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(ins GPRNoX0:$rs1, simm26:$imm), opcodestr,
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"$rd, $rs1, $imm">;
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
@@ -435,6 +469,20 @@ let Predicates = [HasVendorXqcilo, IsRV32], DecoderNamespace = "Xqcilo" in {
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def QC_E_SW : QCIRVInstESStore<0b110, 0b11, "qc.e.sw">;
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} // Predicates = [HasVendorXqcilo, IsRV32], DecoderNamespace = "Xqcilo"
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let Predicates = [HasVendorXqcilia, IsRV32], DecoderNamespace = "Xqcilia" in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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def QC_E_XORAI : QCIRVInstEAI<0b001, 0b0, "qc.e.xorai">;
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def QC_E_ORAI : QCIRVInstEAI<0b001, 0b1, "qc.e.orai" >;
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def QC_E_ADDAI : QCIRVInstEAI<0b010, 0b0, "qc.e.addai">;
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def QC_E_ANDAI : QCIRVInstEAI<0b010, 0b1, "qc.e.andai">;
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def QC_E_XORI : QCIRVInstEI<0b011, 0b00, "qc.e.xori">;
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def QC_E_ORI : QCIRVInstEI<0b011, 0b01, "qc.e.ori" >;
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def QC_E_ADDI : QCIRVInstEI<0b011, 0b10, "qc.e.addi">;
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def QC_E_ANDI : QCIRVInstEI<0b011, 0b11, "qc.e.andi">;
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} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
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} // Predicates = [HasVendorXqcilia, IsRV32], DecoderNamespace = "Xqcilia"
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//===----------------------------------------------------------------------===//
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// Aliases
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//===----------------------------------------------------------------------===//

‎llvm/lib/TargetParser/RISCVISAInfo.cpp

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@@ -742,8 +742,9 @@ Error RISCVISAInfo::checkDependency() {
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bool HasZvl = MinVLen != 0;
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bool HasZcmt = Exts.count("zcmt") != 0;
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static constexpr StringLiteral XqciExts[] = {
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{"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"}, {"xqcics"},
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{"xqcicsr"}, {"xqciint"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
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{"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"},
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{"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcilia"},
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{"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
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if (HasI && HasE)
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return getIncompatibleError("i", "e");

‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -88,6 +88,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciint %s -o - | FileCheck --check-prefix=RV32XQCIINT %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilia %s -o - | FileCheck --check-prefix=RV32XQCILIA %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo %s -o - | FileCheck --check-prefix=RV32XQCILO %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
@@ -404,6 +405,7 @@
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; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2"
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; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
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; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p2"
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; RV32XQCILIA: .attribute 5, "rv32i2p1_zca1p0_xqcilia0p2"
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; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2"
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; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2"
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; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"

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