|
29 | 29 | #include "SIMachineFunctionInfo.h" |
30 | 30 | #include "Utils/AMDGPUBaseInfo.h" |
31 | 31 | #include "llvm/ADT/STLExtras.h" |
| 32 | +#include "llvm/CodeGen/CalcSpillWeights.h" |
32 | 33 | #include "llvm/CodeGen/RegisterClassInfo.h" |
33 | 34 | #include "llvm/MC/LaneBitmask.h" |
34 | 35 | #include "llvm/Support/ErrorHandling.h" |
@@ -1633,64 +1634,6 @@ void GCNSchedStage::revertScheduling() { |
1633 | 1634 | DAG.Regions[RegionIdx] = std::pair(DAG.RegionBegin, DAG.RegionEnd); |
1634 | 1635 | } |
1635 | 1636 |
|
1636 | | -bool PreRARematStage::allUsesAvailableAt(const MachineInstr *InstToRemat, |
1637 | | - SlotIndex OriginalIdx, |
1638 | | - SlotIndex RematIdx) const { |
1639 | | - |
1640 | | - LiveIntervals *LIS = DAG.LIS; |
1641 | | - MachineRegisterInfo &MRI = DAG.MRI; |
1642 | | - OriginalIdx = OriginalIdx.getRegSlot(true); |
1643 | | - RematIdx = std::max(RematIdx, RematIdx.getRegSlot(true)); |
1644 | | - for (const MachineOperand &MO : InstToRemat->operands()) { |
1645 | | - if (!MO.isReg() || !MO.getReg() || !MO.readsReg()) |
1646 | | - continue; |
1647 | | - |
1648 | | - if (!MO.getReg().isVirtual()) { |
1649 | | - // Do not attempt to reason about PhysRegs |
1650 | | - // TODO: better analysis of PhysReg livness |
1651 | | - if (!DAG.MRI.isConstantPhysReg(MO.getReg()) && |
1652 | | - !DAG.TII->isIgnorableUse(MO)) |
1653 | | - return false; |
1654 | | - |
1655 | | - // Constant PhysRegs and IgnorableUses are okay |
1656 | | - continue; |
1657 | | - } |
1658 | | - |
1659 | | - LiveInterval &LI = LIS->getInterval(MO.getReg()); |
1660 | | - const VNInfo *OVNI = LI.getVNInfoAt(OriginalIdx); |
1661 | | - assert(OVNI); |
1662 | | - |
1663 | | - // Don't allow rematerialization immediately after the original def. |
1664 | | - // It would be incorrect if InstToRemat redefines the register. |
1665 | | - // See PR14098. |
1666 | | - if (SlotIndex::isSameInstr(OriginalIdx, RematIdx)) |
1667 | | - return false; |
1668 | | - |
1669 | | - if (OVNI != LI.getVNInfoAt(RematIdx)) |
1670 | | - return false; |
1671 | | - |
1672 | | - // Check that subrange is live at RematIdx. |
1673 | | - if (LI.hasSubRanges()) { |
1674 | | - const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo(); |
1675 | | - unsigned SubReg = MO.getSubReg(); |
1676 | | - LaneBitmask LM = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) |
1677 | | - : MRI.getMaxLaneMaskForVReg(MO.getReg()); |
1678 | | - for (LiveInterval::SubRange &SR : LI.subranges()) { |
1679 | | - if ((SR.LaneMask & LM).none()) |
1680 | | - continue; |
1681 | | - if (!SR.liveAt(RematIdx)) |
1682 | | - return false; |
1683 | | - |
1684 | | - // Early exit if all used lanes are checked. No need to continue. |
1685 | | - LM &= ~SR.LaneMask; |
1686 | | - if (LM.none()) |
1687 | | - break; |
1688 | | - } |
1689 | | - } |
1690 | | - } |
1691 | | - return true; |
1692 | | -} |
1693 | | - |
1694 | 1637 | bool PreRARematStage::canIncreaseOccupancyOrReduceSpill() { |
1695 | 1638 | const Function &F = MF.getFunction(); |
1696 | 1639 |
|
@@ -1812,9 +1755,9 @@ bool PreRARematStage::canIncreaseOccupancyOrReduceSpill() { |
1812 | 1755 | // Do not rematerialize an instruction it it uses registers that aren't |
1813 | 1756 | // available at its use. This ensures that we are not extending any live |
1814 | 1757 | // range while rematerializing. |
1815 | | - SlotIndex DefIdx = DAG.LIS->getInstructionIndex(DefMI); |
1816 | 1758 | SlotIndex UseIdx = DAG.LIS->getInstructionIndex(*UseMI).getRegSlot(true); |
1817 | | - if (!allUsesAvailableAt(&DefMI, DefIdx, UseIdx)) |
| 1759 | + if (!VirtRegAuxInfo::allUsesAvailableAt(&DefMI, UseIdx, *DAG.LIS, DAG.MRI, |
| 1760 | + *DAG.TII)) |
1818 | 1761 | continue; |
1819 | 1762 |
|
1820 | 1763 | REMAT_DEBUG(dbgs() << "Region " << I << ": remat instruction " << DefMI); |
|
0 commit comments