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[AMDGPU] Remove ApproxFuncFPMath uses (#155578)
One of options in `resetTargetOptions`, this removes `ApproxFuncFPMath` in AMDGPU part.
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7 files changed

+8
-385
lines changed

7 files changed

+8
-385
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp‎

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2650,10 +2650,7 @@ static bool valueIsKnownNeverF32Denorm(SDValue Src) {
26502650

26512651
bool AMDGPUTargetLowering::allowApproxFunc(const SelectionDAG &DAG,
26522652
SDNodeFlags Flags) {
2653-
if (Flags.hasApproximateFuncs())
2654-
return true;
2655-
auto &Options = DAG.getTarget().Options;
2656-
return Options.ApproxFuncFPMath;
2653+
return Flags.hasApproximateFuncs();
26572654
}
26582655

26592656
bool AMDGPUTargetLowering::needsDenormHandlingF32(const SelectionDAG &DAG,
@@ -2775,8 +2772,7 @@ SDValue AMDGPUTargetLowering::LowerFLOGCommon(SDValue Op,
27752772
assert(IsLog10 || Op.getOpcode() == ISD::FLOG);
27762773

27772774
const auto &Options = getTargetMachine().Options;
2778-
if (VT == MVT::f16 || Flags.hasApproximateFuncs() ||
2779-
Options.ApproxFuncFPMath) {
2775+
if (VT == MVT::f16 || Flags.hasApproximateFuncs()) {
27802776

27812777
if (VT == MVT::f16 && !Subtarget->has16BitInsts()) {
27822778
// Log and multiply in f32 is good enough for f16.

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp‎

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3414,10 +3414,7 @@ static bool valueIsKnownNeverF32Denorm(const MachineRegisterInfo &MRI,
34143414
}
34153415

34163416
static bool allowApproxFunc(const MachineFunction &MF, unsigned Flags) {
3417-
if (Flags & MachineInstr::FmAfn)
3418-
return true;
3419-
const auto &Options = MF.getTarget().Options;
3420-
return Options.ApproxFuncFPMath;
3417+
return Flags & MachineInstr::FmAfn;
34213418
}
34223419

34233420
static bool needsDenormHandlingF32(const MachineFunction &MF, Register Src,
@@ -3522,8 +3519,7 @@ bool AMDGPULegalizerInfo::legalizeFlogCommon(MachineInstr &MI,
35223519
const AMDGPUTargetMachine &TM =
35233520
static_cast<const AMDGPUTargetMachine &>(MF.getTarget());
35243521

3525-
if (Ty == F16 || MI.getFlag(MachineInstr::FmAfn) ||
3526-
TM.Options.ApproxFuncFPMath) {
3522+
if (Ty == F16 || MI.getFlag(MachineInstr::FmAfn)) {
35273523
if (Ty == F16 && !ST.has16BitInsts()) {
35283524
Register LogVal = MRI.createGenericVirtualRegister(F32);
35293525
auto PromoteSrc = B.buildFPExt(F32, X);

‎llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1274,13 +1274,13 @@ define float @v_sqrt_f32_afn_nnan_ninf_nsz(float %x) {
12741274
ret float %result
12751275
}
12761276

1277-
define float @v_sqrt_f32__approx_func_fp_math(float %x) #2 {
1277+
define float @v_sqrt_f32__approx_func_fp_math(float %x) {
12781278
; GCN-LABEL: v_sqrt_f32__approx_func_fp_math:
12791279
; GCN: ; %bb.0:
12801280
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
12811281
; GCN-NEXT: v_sqrt_f32_e32 v0, v0
12821282
; GCN-NEXT: s_setpc_b64 s[30:31]
1283-
%result = call nsz float @llvm.sqrt.f32(float %x)
1283+
%result = call afn nsz float @llvm.sqrt.f32(float %x)
12841284
ret float %result
12851285
}
12861286

@@ -1290,7 +1290,7 @@ define float @v_sqrt_f32__enough_unsafe_attrs(float %x) #3 {
12901290
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
12911291
; GCN-NEXT: v_sqrt_f32_e32 v0, v0
12921292
; GCN-NEXT: s_setpc_b64 s[30:31]
1293-
%result = call nsz float @llvm.sqrt.f32(float %x)
1293+
%result = call afn nsz float @llvm.sqrt.f32(float %x)
12941294
ret float %result
12951295
}
12961296

@@ -4761,8 +4761,7 @@ declare { float, i32 } @llvm.frexp.f32.i32(float) #0
47614761

47624762
attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
47634763
attributes #1 = { convergent nounwind willreturn memory(none) }
4764-
attributes #2 = { "approx-func-fp-math"="true" }
4765-
attributes #3 = { "approx-func-fp-math"="true" "no-nans-fp-math"="true" "no-infs-fp-math"="true" }
4764+
attributes #3 = { "no-nans-fp-math"="true" "no-infs-fp-math"="true" }
47664765
attributes #5 = { "no-infs-fp-math"="true" }
47674766

47684767
!0 = !{float 0.5}

‎llvm/test/CodeGen/AMDGPU/llvm.exp.ll‎

Lines changed: 0 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -3227,72 +3227,6 @@ define float @v_exp_f32_fast(float %in) {
32273227
ret float %result
32283228
}
32293229

3230-
define float @v_exp_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
3231-
; GCN-SDAG-LABEL: v_exp_f32_approx_fn_attr:
3232-
; GCN-SDAG: ; %bb.0:
3233-
; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3234-
; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
3235-
; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v0
3236-
; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
3237-
; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
3238-
; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
3239-
; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
3240-
; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
3241-
; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
3242-
; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
3243-
;
3244-
; GCN-GISEL-LABEL: v_exp_f32_approx_fn_attr:
3245-
; GCN-GISEL: ; %bb.0:
3246-
; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3247-
; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
3248-
; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0
3249-
; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
3250-
; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
3251-
; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
3252-
; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
3253-
; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
3254-
; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
3255-
; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
3256-
;
3257-
; SI-SDAG-LABEL: v_exp_f32_approx_fn_attr:
3258-
; SI-SDAG: ; %bb.0:
3259-
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3260-
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
3261-
; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v0
3262-
; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
3263-
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
3264-
; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
3265-
; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
3266-
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
3267-
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
3268-
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
3269-
;
3270-
; SI-GISEL-LABEL: v_exp_f32_approx_fn_attr:
3271-
; SI-GISEL: ; %bb.0:
3272-
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3273-
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
3274-
; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0
3275-
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
3276-
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
3277-
; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
3278-
; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
3279-
; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
3280-
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
3281-
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
3282-
;
3283-
; R600-LABEL: v_exp_f32_approx_fn_attr:
3284-
; R600: ; %bb.0:
3285-
; R600-NEXT: CF_END
3286-
; R600-NEXT: PAD
3287-
;
3288-
; CM-LABEL: v_exp_f32_approx_fn_attr:
3289-
; CM: ; %bb.0:
3290-
; CM-NEXT: CF_END
3291-
; CM-NEXT: PAD
3292-
%result = call float @llvm.exp.f32(float %in)
3293-
ret float %result
3294-
}
3295-
32963230
define float @v_exp_f32_ninf(float %in) {
32973231
; VI-SDAG-LABEL: v_exp_f32_ninf:
32983232
; VI-SDAG: ; %bb.0:

‎llvm/test/CodeGen/AMDGPU/llvm.exp10.ll‎

Lines changed: 0 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -3235,78 +3235,6 @@ define float @v_exp10_f32_fast(float %in) {
32353235
ret float %result
32363236
}
32373237

3238-
define float @v_exp10_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
3239-
; GCN-SDAG-LABEL: v_exp10_f32_approx_fn_attr:
3240-
; GCN-SDAG: ; %bb.0:
3241-
; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3242-
; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc217b818
3243-
; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v0
3244-
; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
3245-
; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
3246-
; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0
3247-
; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0
3248-
; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v1
3249-
; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
3250-
; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
3251-
; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0
3252-
; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
3253-
; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
3254-
;
3255-
; GCN-GISEL-LABEL: v_exp10_f32_approx_fn_attr:
3256-
; GCN-GISEL: ; %bb.0:
3257-
; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3258-
; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
3259-
; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0
3260-
; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
3261-
; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
3262-
; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
3263-
; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
3264-
; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
3265-
; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
3266-
; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
3267-
;
3268-
; SI-SDAG-LABEL: v_exp10_f32_approx_fn_attr:
3269-
; SI-SDAG: ; %bb.0:
3270-
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3271-
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b818
3272-
; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v0
3273-
; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
3274-
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
3275-
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0
3276-
; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0
3277-
; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
3278-
; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
3279-
; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
3280-
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0
3281-
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
3282-
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
3283-
;
3284-
; SI-GISEL-LABEL: v_exp10_f32_approx_fn_attr:
3285-
; SI-GISEL: ; %bb.0:
3286-
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3287-
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
3288-
; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0
3289-
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
3290-
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
3291-
; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
3292-
; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
3293-
; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
3294-
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
3295-
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
3296-
;
3297-
; R600-LABEL: v_exp10_f32_approx_fn_attr:
3298-
; R600: ; %bb.0:
3299-
; R600-NEXT: CF_END
3300-
; R600-NEXT: PAD
3301-
;
3302-
; CM-LABEL: v_exp10_f32_approx_fn_attr:
3303-
; CM: ; %bb.0:
3304-
; CM-NEXT: CF_END
3305-
; CM-NEXT: PAD
3306-
%result = call float @llvm.exp10.f32(float %in)
3307-
ret float %result
3308-
}
3309-
33103238
define float @v_exp10_f32_ninf(float %in) {
33113239
; VI-SDAG-LABEL: v_exp10_f32_ninf:
33123240
; VI-SDAG: ; %bb.0:

‎llvm/test/CodeGen/AMDGPU/llvm.log.ll‎

Lines changed: 0 additions & 115 deletions
Original file line numberDiff line numberDiff line change
@@ -3076,121 +3076,6 @@ define float @v_log_f32_fast(float %in) {
30763076
ret float %result
30773077
}
30783078

3079-
define float @v_log_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
3080-
; SI-SDAG-LABEL: v_log_f32_approx_fn_attr:
3081-
; SI-SDAG: ; %bb.0:
3082-
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3083-
; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
3084-
; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
3085-
; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
3086-
; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
3087-
; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
3088-
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
3089-
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
3090-
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317218
3091-
; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
3092-
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
3093-
;
3094-
; SI-GISEL-LABEL: v_log_f32_approx_fn_attr:
3095-
; SI-GISEL: ; %bb.0:
3096-
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3097-
; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
3098-
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
3099-
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
3100-
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
3101-
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
3102-
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
3103-
; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
3104-
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
3105-
;
3106-
; VI-SDAG-LABEL: v_log_f32_approx_fn_attr:
3107-
; VI-SDAG: ; %bb.0:
3108-
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3109-
; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
3110-
; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
3111-
; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
3112-
; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
3113-
; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
3114-
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
3115-
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
3116-
; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
3117-
; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
3118-
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
3119-
;
3120-
; VI-GISEL-LABEL: v_log_f32_approx_fn_attr:
3121-
; VI-GISEL: ; %bb.0:
3122-
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3123-
; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
3124-
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
3125-
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
3126-
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
3127-
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
3128-
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v2
3129-
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
3130-
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
3131-
;
3132-
; GFX900-SDAG-LABEL: v_log_f32_approx_fn_attr:
3133-
; GFX900-SDAG: ; %bb.0:
3134-
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3135-
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
3136-
; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
3137-
; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
3138-
; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
3139-
; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
3140-
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
3141-
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
3142-
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317218
3143-
; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
3144-
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
3145-
;
3146-
; GFX900-GISEL-LABEL: v_log_f32_approx_fn_attr:
3147-
; GFX900-GISEL: ; %bb.0:
3148-
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3149-
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
3150-
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
3151-
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
3152-
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
3153-
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
3154-
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
3155-
; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
3156-
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
3157-
;
3158-
; GFX1100-SDAG-LABEL: v_log_f32_approx_fn_attr:
3159-
; GFX1100-SDAG: ; %bb.0:
3160-
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3161-
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
3162-
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
3163-
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0xc1b17218, vcc_lo
3164-
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
3165-
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
3166-
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
3167-
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
3168-
; GFX1100-SDAG-NEXT: v_fmamk_f32 v0, v0, 0x3f317218, v1
3169-
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
3170-
;
3171-
; GFX1100-GISEL-LABEL: v_log_f32_approx_fn_attr:
3172-
; GFX1100-GISEL: ; %bb.0:
3173-
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3174-
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
3175-
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
3176-
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, vcc_lo
3177-
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
3178-
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
3179-
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
3180-
;
3181-
; R600-LABEL: v_log_f32_approx_fn_attr:
3182-
; R600: ; %bb.0:
3183-
; R600-NEXT: CF_END
3184-
; R600-NEXT: PAD
3185-
;
3186-
; CM-LABEL: v_log_f32_approx_fn_attr:
3187-
; CM: ; %bb.0:
3188-
; CM-NEXT: CF_END
3189-
; CM-NEXT: PAD
3190-
%result = call float @llvm.log.f32(float %in)
3191-
ret float %result
3192-
}
3193-
31943079
define float @v_log_f32_ninf(float %in) {
31953080
; SI-SDAG-LABEL: v_log_f32_ninf:
31963081
; SI-SDAG: ; %bb.0:

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